Lines Matching full:ordering
87 (*) Assumed minimum execution ordering model.
137 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
365 ordering over the memory operations on either side of the barrier.
387 A write barrier is a partial ordering on stores only; it is not required
407 A data dependency barrier is a partial ordering on interdependent loads
421 showing the ordering constraints.
441 A read barrier is a partial ordering on loads only; it is not required to
458 A general memory barrier is a partial ordering over both loads and stores.
642 of dependency ordering is to -prevent- writes to the data structure, along
645 naturally occurring ordering prevents such records from being lost.
648 Note well that the ordering provided by a data dependency is local to
691 However, stores are not speculated. This means that ordering -is- provided
704 Either can result in highly counterintuitive effects on ordering.
716 It is tempting to try to enforce ordering on identical stores on both
735 WRITE_ONCE(b, 1); /* BUG: No ordering vs. load from a!!! */
748 Therefore, if you need ordering in this example, you need explicit
761 ordering is guaranteed only when the stores differ, for example:
796 Given this transformation, the CPU is not required to respect the ordering
800 relying on this ordering, you should make sure that MAX is greater than
846 WRITE_ONCE(c, 1); /* BUG: No ordering against the read from 'a'. */
848 It is tempting to argue that there in fact is ordering because the
870 Note well that the ordering provided by a control dependency is local
878 However, they do -not- guarantee any other sort of ordering:
880 later anything. If you need these other forms of ordering,
897 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
1160 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1354 Multicopy atomicity is a deeply intuitive notion about ordering that is
1418 but can also generate additional ordering that can ensure that -all-
1420 chain of release-acquire pairs do not provide this additional ordering,
1467 However, the ordering provided by a release-acquire chain is local
1488 In particular, it simply reads from its argument with ordering. It does
1497 To reiterate, if your code requires full ordering of all operations,
1830 barrier. Data dependencies do not impose any additional compiler ordering.
1847 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1898 These are for use with consistent memory to guarantee the ordering
1948 in addition to the ordering done by wmb().
1951 to ensure read ordering.
2077 Locks and semaphores may not provide any guarantee of ordering on UP compiled
2233 In terms of memory ordering, these functions all provide the same guarantees of
2285 that does affect memory access ordering on other CPUs, within the context of
2434 CPU, that CPU's dependency ordering logic will take care of everything else.
2466 memory barriers are required to enforce ordering.
2499 address register if ordering rules are sufficiently relaxed:
2504 If ordering rules are relaxed, it must be assumed that accesses done inside an
2516 likely, then interrupt-disabling locks should be used to guarantee ordering.
2528 series of accessor functions that provide various degrees of ordering
2536 ioremap()), the ordering guarantees are as follows:
2576 The ordering properties of __iomem pointers obtained with non-default
2584 ordering guarantees. Specifically, they do not guarantee ordering with
2595 capable of performing DMA. Consequently, they provide only the ordering
2606 internal virtual memory mapping, the portable ordering guarantees
2614 not part of the portable ordering semantics.
2618 As above, the insX() and outsX() accessors provide the same ordering
2634 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2803 (*) the CPU's data cache may affect the ordering, and while cache-coherency
2935 Chapter 5.6: Read/Write Ordering
2938 Chapter 7.1: Memory-Access Ordering
2947 Chapter 7.2: Memory Ordering