Lines Matching full:guarantee

332      of the standard containing this guarantee is Section 3.14, which
382      A write memory barrier gives a guarantee that all the STORE operations
436      A read barrier is a data dependency barrier plus a guarantee that all the
453      A general memory barrier gives a guarantee that all the LOAD and STORE
524 There are certain things that the Linux kernel memory barriers do not guarantee:
526  (*) There is no guarantee that any of the memory accesses specified before a
531  (*) There is no guarantee that issuing a memory barrier on one CPU will have
536  (*) There is no guarantee that a CPU will see the correct order of effects
541  (*) There is no guarantee that some intervening piece of off-the-CPU
878       However, they do -not- guarantee any other sort of ordering:
1249 The guarantee is that the second load will always come up with A == 1 if the
1250 load of B came up with B == 2.  No such guarantee exists for the first load of
1376 CPU 3's load from Y.  In addition, the memory barriers guarantee that
1411 and store, it does not guarantee to order CPU 1's store.  Thus, if this
1834 the value of b before loading a[b]), however there is no guarantee in
1898      These are for use with consistent memory to guarantee the ordering
1925      The dma_rmb() allows us guarantee the device has released ownership
1927      us to guarantee the data is written to the descriptor before the device
1929      wmb() is not needed to guarantee that the cache coherent memory writes
1931      writel_relaxed() does not provide this guarantee and must not be used
1960 This specification is a _minimum_ guarantee; any particular architecture may
2077 Locks and semaphores may not provide any guarantee of ordering on UP compiled
2197 if something is actually awakened, but otherwise there is no such guarantee.
2253 there's no guarantee that the change to event_indicated will be perceived by
2304 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2425 In this case, the barrier makes a guarantee that all memory accesses before the
2427 with respect to the other CPUs on the system.  It does _not_ guarantee that all
2516 likely, then interrupt-disabling locks should be used to guarantee ordering.
2584 	ordering guarantees. Specifically, they do not guarantee ordering with
2805      - there's no guarantee that the coherency management will be propagated in