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5 The following is a summary of the SMBus protocol. It applies to
11 which is a subset from the I2C protocol. Fortunately, many devices use
14 If you write a driver for some I2C device, please try to use the SMBus
21 Below is a list of SMBus protocol operations, and the functions executing
23 don't match these function names. For some of the operations which pass a
25 a different protocol operation entirely.
27 Each transaction type corresponds to a functionality flag. Before calling a
28 transaction function, a device driver should always check (just once) for
41 A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
43 get a 10 bit I2C address.
44 Comm (8 bits) Command byte, a data byte which often selects a register on
46 Data (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh
48 Count (8 bits) A data byte containing the length of a block operation.
58 This sends a single bit to the device, at the place of the Rd/Wr bit::
60 S Addr Rd/Wr [A] P
70 This reads a single byte from a device, without specifying a device
72 others, it is a shorthand if you want to read the same register as in
75 S Addr Rd [A] [Data] NA P
85 This operation is the reverse of Receive Byte: it sends a single byte
86 to a device. See Receive Byte for more information.
90 S Addr Wr [A] Data [A] P
100 This reads a single byte from a device, from a designated register.
103 S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P
113 This operation is very like Read Byte; again, data is read from a
114 device, from a designated register that is specified through the Comm
115 byte. But this time, the data is a complete word (16 bits)::
117 S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
131 This writes a single byte to a device, to a designated register. The
137 S Addr Wr [A] Comm [A] Data [A] P
148 of data are written to a device, to the designated register that is
151 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
163 This command selects a device register (through the Comm byte), sends
166 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
167 S Addr Rd [A] [DataLow] A [DataHigh] NA P
177 This command reads a block of up to 32 bytes from a device, from a
183 S Addr Wr [A] Comm [A]
184 S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
195 a device, to a designated register that is specified through the
200 S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
211 This command selects a device register (through the Comm byte), sends
214 S Addr Wr [A] Comm [A] Count [A] Data [A] ...
215 S Addr Rd [A] [Count] A [Data] ... A P
223 This command is sent from a SMBus device acting as a master to the
224 SMBus host acting as a slave.
230 [S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]
236 * I2C bus drivers trigger SMBus Host Notify by a call to
239 client->irq assigned to a Host Notify IRQ if noone else specified an other.
249 PEC adds a CRC-8 error-checking byte to transfers using it, immediately
257 the specification. It is a higher-layer protocol which uses the
270 The SMBus alert protocol allows several SMBus slave devices to share a
286 and Write operations, except these do not have a Count byte. They are
291 but the SMBus layer places a limit of 32 bytes.
299 This command reads a block of bytes from a device, from a
302 S Addr Wr [A] Comm [A]
303 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
314 a device, to a designated register that is specified through the
320 S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P