Lines Matching +full:j721e +full:- +full:usb
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
10 - Roger Quadros <rogerq@ti.com>
15 - const: ti,j721e-usb
20 power-domains:
23 the USB device id value. See,
24 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
31 clock-names:
33 - const: ref
34 - const: lpm
36 ti,usb2-only:
40 for USB.
43 ti,vbus-divider:
45 Should be present if USB VBUS line is connected to the
49 assigned-clocks:
52 assigned-clock-parents:
55 '#address-cells':
58 '#size-cells':
62 "^usb@":
66 - compatible
67 - reg
68 - power-domains
69 - clocks
70 - clock-names
75 - |
76 #include <dt-bindings/soc/ti,sci_pm_domain.h>
77 #include <dt-bindings/interrupt-controller/arm-gic.h>
80 #address-cells = <2>;
81 #size-cells = <2>;
84 compatible = "ti,j721e-usb";
86 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
88 clock-names = "ref", "lpm";
89 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
90 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
91 #address-cells = <2>;
92 #size-cells = <2>;
94 usb@6000000 {
99 reg-names = "otg", "xhci", "dev";
103 interrupt-names = "host",
106 maximum-speed = "super-speed";