Lines Matching +full:sdm845 +full:- +full:dwc3
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Manu Gautam <mgautam@codeaurora.org>
15 - enum:
16 - qcom,msm8996-dwc3
17 - qcom,msm8998-dwc3
18 - qcom,sc7180-dwc3
19 - qcom,sdm845-dwc3
20 - const: qcom,dwc3
26 "#address-cells":
29 "#size-cells":
34 power-domains:
40 A list of phandle and clock-specifier pairs for the clocks
41 listed in clock-names.
43 - description: System Config NOC clock.
44 - description: Master/Core clock, has to be >= 125 MHz
46 - description: System bus AXI clock.
47 - description: Mock utmi clock needed for ITP/SOF generation
49 - description: Sleep clock, used for wakeup when
52 clock-names:
54 - const: cfg_noc
55 - const: core
56 - const: iface
57 - const: mock_utmi
58 - const: sleep
60 assigned-clocks:
62 - description: Phandle and clock specifier of MOCK_UTMI_CLK.
63 - description: Phandle and clock specifoer of MASTER_CLK.
65 assigned-clock-rates:
67 - description: Must be 19.2MHz (19200000).
68 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
75 interconnect-names:
77 - const: usb-ddr
78 - const: apps-usb
82 - description: The interrupt that is asserted
84 - description: The interrupt that is asserted
86 - description: Wakeup event on DM line.
87 - description: Wakeup event on DP line.
89 interrupt-names:
91 - const: hs_phy_irq
92 - const: ss_phy_irq
93 - const: dm_hs_phy_irq
94 - const: dp_hs_phy_irq
96 qcom,select-utmi-as-pipe-clk:
99 Used when dwc3 operates without SSPHY and only
106 "^dwc3@[0-9a-f]+$":
109 A child node must exist to represent the core DWC3 IP block
110 The content of the node is defined in dwc3.txt.
113 - compatible
114 - reg
115 - "#address-cells"
116 - "#size-cells"
117 - ranges
118 - power-domains
119 - clocks
120 - clock-names
121 - interrupts
122 - interrupt-names
127 - |
128 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
129 #include <dt-bindings/interrupt-controller/arm-gic.h>
130 #include <dt-bindings/interrupt-controller/irq.h>
132 #address-cells = <2>;
133 #size-cells = <2>;
136 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
139 #address-cells = <2>;
140 #size-cells = <2>;
147 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
150 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
152 assigned-clock-rates = <19200000>, <150000000>;
158 interrupt-names = "hs_phy_irq", "ss_phy_irq",
161 power-domains = <&gcc USB30_PRIM_GDSC>;
165 dwc3@a600000 {
166 compatible = "snps,dwc3";
173 phy-names = "usb2-phy", "usb3-phy";