Lines Matching +full:single +full:- +full:cell

4 controller with wrapping arbitration logic to allow for multiple on-chip
5 devices to control a single SPMI master.
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names  : must contain:
19      "core" - core registers
20      "intr" - interrupt controller registers
21      "cnfg" - configuration registers
23      "chnls"  - tx-channel per virtual slave registers.
24      "obsrvr" - rx-channel (called observer) per virtual slave registers.
26 - reg : address + size pairs describing the PMIC arb register sets; order must
27         correspond with the order of entries in reg-names
28 - #address-cells : must be set to 2
29 - #size-cells : must be set to 0
30 - qcom,ee : indicates the active Execution Environment identifier (0-5)
31 - qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
32 - interrupts : interrupt list for the PMIC Arb controller, must contain a
33                single interrupt entry for the peripheral interrupt
34 - interrupt-names : corresponding interrupt names for the interrupts
36      "periph_irq" - summary interrupt for PMIC peripherals
37 - interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
38 - #interrupt-cells :  must be set to 4. Interrupts are specified as a 4-tuple:
39     cell 1: slave ID for the requested interrupt (0-15)
40     cell 2: peripheral ID for requested interrupt (0-255)
41     cell 3: the requested peripheral interrupt (0-7)
42     cell 4: interrupt flags indicating level-sense information, as defined in
43             dt-bindings/interrupt-controller/irq.h
48 		compatible = "qcom,spmi-pmic-arb";
49 		reg-names = "core", "intr", "cnfg";
54 		interrupt-names = "periph_irq";
60 		#address-cells = <2>;
61 		#size-cells = <0>;
63 		interrupt-controller;
64 		#interrupt-cells = <4>;