Lines Matching full:khz
16 In order to support 48KHz and 44.1KHz family of sampling rates the parent
17 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
18 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
22 48KHz family:
26 44.1KHz family:
31 48KHz family:
84 - description: Parent for CPB_McASP auxclk (for 48KHz)
85 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
87 - description: Parent for CPB_SCKI clock (for 48KHz)
88 - description: Parent for CPB_SCKI clock (for 44.1KHz)
111 - description: Parent for CPB_McASP auxclk (for 48KHz)
113 - description: Parent for CPB_SCKI clock (for 48KHz)