Lines Matching full:topckgen
69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
79 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
80 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
81 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
82 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
83 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
84 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
139 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
140 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
141 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
143 <&topckgen CLK_TOP_AUD2PLL_90M>;