Lines Matching +full:smem +full:- +full:state +full:- +full:names

1 Qualcomm Shared Memory State Machine
3 The Shared Memory State Machine facilitates broadcasting of single bit state
5 assigned 32 bits of state that can be modified. A processor can through a
9 - compatible:
15 - qcom,ipc-N:
17 	Value type: <prop-encoded-array>
20 		    - phandle to a syscon node representing the apcs registers
21 		    - u32 representing offset to the register within the syscon
22 		    - u32 representing the ipc bit within the register
24 - qcom,local-host:
32 - #address-cells:
37 - #size-cells:
43 Each processor's state bits are described by a subnode of the smsm device node.
44 Nodes can either be flagged as an interrupt-controller to denote a remote
45 processor's state bits or the local processors bits.  The node names are not
48 - reg:
54 - #qcom,smem-state-cells:
57 	Definition: must be 1 - denotes bit number
59 - interrupt-controller:
62 	Definition: marks the entry as a interrupt-controller and the state bits
65 - #interrupt-cells:
68 	Definition: must be 2 - denotes bit number and IRQ flags
70 - interrupts:
72 	Value type: <prop-encoded-array>
74 		    to signal changes of its state bits
78 The following example shows the SMEM setup for controlling properties of the
79 wireless processor, defined from the 8974 apps processor's point-of-view. It
86 	#address-cells = <1>;
87 	#size-cells = <0>;
89 	qcom,ipc-3 = <&apcs 8 19>;
94 		#qcom,smem-state-cells = <1>;
101 		interrupt-controller;
102 		#interrupt-cells = <2>;