Lines Matching +full:used +full:- +full:by +full:- +full:rtas
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
14 - if:
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
21 - if:
24 const: mrvl,mmp-uart
27 reg-shift:
30 - reg-shift
31 - if:
36 - enum:
37 - ns8250
38 - ns16450
39 - ns16550
40 - ns16550a
43 - required: [ clock-frequency ]
44 - required: [ clocks ]
49 - const: ns8250
50 - const: ns16450
51 - const: ns16550
52 - const: ns16550a
53 - const: ns16850
54 - const: aspeed,ast2400-vuart
55 - const: aspeed,ast2500-vuart
56 - const: intel,xscale-uart
57 - const: mrvl,pxa-uart
58 - const: nuvoton,npcm750-uart
59 - const: nvidia,tegra20-uart
60 - const: nxp,lpc3220-uart
61 - items:
62 - enum:
63 - altr,16550-FIFO32
64 - altr,16550-FIFO64
65 - altr,16550-FIFO128
66 - fsl,16550-FIFO64
67 - fsl,ns16550
68 - andestech,uart16550
69 - nxp,lpc1850-uart
70 - opencores,uart16550-rtlsvn105
71 - ti,da830-uart
72 - const: ns16550a
73 - items:
74 - enum:
75 - ns16750
76 - cavium,octeon-3860-uart
77 - xlnx,xps-uart16550-2.00.b
78 - ralink,rt2880-uart
79 - enum:
80 - ns16550 # Deprecated, unless the FIFO really is broken
81 - ns16550a
82 - items:
83 - enum:
84 - ralink,mt7620a-uart
85 - ralink,rt3052-uart
86 - ralink,rt3883-uart
87 - const: ralink,rt2880-uart
88 - enum:
89 - ns16550 # Deprecated, unless the FIFO really is broken
90 - ns16550a
91 - items:
92 - enum:
93 - mediatek,mt7622-btif
94 - mediatek,mt7623-btif
95 - const: mediatek,mtk-btif
96 - items:
97 - enum:
98 - mediatek,mt7622-btif
99 - mediatek,mt7623-btif
100 - const: mediatek,mtk-btif
101 - items:
102 - const: mrvl,mmp-uart
103 - const: intel,xscale-uart
104 - items:
105 - enum:
106 - nvidia,tegra30-uart
107 - nvidia,tegra114-uart
108 - nvidia,tegra124-uart
109 - nvidia,tegra186-uart
110 - nvidia,tegra194-uart
111 - nvidia,tegra210-uart
112 - const: nvidia,tegra20-uart
120 clock-frequency: true
128 current-speed:
132 reg-offset:
136 reg-shift:
137 description: Quantity to shift the register offsets by.
139 reg-io-width:
142 device. There are some systems that require 32-bit accesses to the
145 used-by-rtas:
148 Set to indicate that the port is in use by the OpenFirmware RTAS and
151 no-loopback-test:
156 fifo-size:
160 auto-flow-control:
167 tx-threshold:
173 overrun-throttle-ms:
177 rts-gpios: true
178 cts-gpios: true
179 dtr-gpios: true
180 dsr-gpios: true
181 rng-gpios: true
182 dcd-gpios: true
184 aspeed,sirq-polarity-sense:
185 $ref: /schemas/types.yaml#/definitions/phandle-array
187 Phandle to aspeed,ast2500-scu compatible syscon alongside register
190 applicable to aspeed,ast2500-vuart.
193 - reg
194 - interrupts
199 - |
204 reg-shift = <2>;
205 clock-frequency = <48000000>;
207 - |
208 #include <dt-bindings/gpio/gpio.h>
213 clock-frequency = <48000000>;
214 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
215 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
216 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
217 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
218 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
219 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
221 - |
222 #include <dt-bindings/clock/aspeed-clock.h>
224 compatible = "aspeed,ast2500-vuart";
226 reg-shift = <2>;
229 no-loopback-test;
230 aspeed,sirq-polarity-sense = <&syscon 0x70 25>;