Lines Matching +full:sense +full:- +full:mode

3 PSC in UART mode
4 ----------------
6 For PSC in UART mode the needed PSC serial devices
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15  - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
17  - reg : Offset and length of the register set for the PSC device
18  - interrupts : <a b> where a is the interrupt number of the
20    encoding of the sense and level information for the interrupt.
23  - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
24  - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
26 PSC in SPI mode
27 ---------------
29 Similar to the UART mode a PSC can be operated in SPI mode. The compatible used
30 for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
32 fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible
35 fsl,mpc512x-psc-fifo node
36 -------------------------
39  - compatible : Should be "fsl,<soc>-psc-fifo"
41  - reg : Offset and length of the register set for the PSC
43  - interrupts : <a b> where a is the interrupt number of the
45    encoding of the sense and level information for the interrupt.
48  - clocks : specifies the clock needed to operate the fifo controller
49  - clock-names : name(s) for the clock(s) listed in clocks
51 Example for a board using PSC0 and PSC1 devices in serial mode:
54 	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
55 	cell-index = <0>;
58 	interrupt-parent = < &ipic >;
59 	fsl,rx-fifo-size = <16>;
60 	fsl,tx-fifo-size = <16>;
64 	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
65 	cell-index = <1>;
68 	interrupt-parent = < &ipic >;
69 	fsl,rx-fifo-size = <16>;
70 	fsl,tx-fifo-size = <16>;
74 	compatible = "fsl,mpc5121-psc-fifo";
77 	interrupt-parent = < &ipic >;