Lines Matching +full:0 +full:x5000000
63 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
77 "^pll[0|1]-refclk$":
88 const: 0
114 const: 0
134 const: 0
148 "^serdes@[0-9a-f]+$":
182 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
186 ranges = <0x5000000 0x5000000 0x10000>;
190 #clock-cells = <0>;
196 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
197 #clock-cells = <0>;
199 assigned-clock-parents = <&k3_clks 293 0>;
204 #clock-cells = <0>;
209 #clock-cells = <0>;
213 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
215 #clock-cells = <0>;
223 reg = <0x5000000 0x10000>;
225 #size-cells = <0>;
226 resets = <&serdes_wiz0 0>;