Lines Matching +full:pcie +full:- +full:phy
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy
24 description: PHY register region (offset and length)
26 "#phy-cells":
33 clock-names:
35 - items: # for Pro5
36 - const: gio
37 - const: link
38 - const: link # for others
44 reset-names:
46 - items: # for Pro5
47 - const: gio
48 - const: link
49 - const: link # for others
53 description: A phandle to system control to set configurations for phy
56 - compatible
57 - reg
58 - "#phy-cells"
59 - clocks
60 - clock-names
61 - resets
62 - reset-names
67 - |
68 pcie_phy: phy@66038000 {
69 compatible = "socionext,uniphier-ld20-pcie-phy";
71 #phy-cells = <0>;
72 clock-names = "link";
74 reset-names = "link";