Lines Matching full:phy
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
14 In case of exynos5433 compatible PHY:
20 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
21 the PHY specifier identifies the PHY and its meaning is as follows:
26 "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
27 supports additional fifth PHY:
30 Samsung Exynos SoC series Display Port PHY
35 - "samsung,exynos5250-dp-video-phy"
36 - "samsung,exynos5420-dp-video-phy"
39 - #phy-cells : from the generic PHY bindings, must be 0;
41 Samsung S5P/Exynos SoC series USB PHY
46 - "samsung,exynos3250-usb2-phy"
47 - "samsung,exynos4210-usb2-phy"
48 - "samsung,exynos4x12-usb2-phy"
49 - "samsung,exynos5250-usb2-phy"
50 - "samsung,s5pv210-usb2-phy"
51 - reg : a list of registers used by phy driver
52 - first and obligatory is the location of phy modules registers
55 - #phy-cells : from the generic phy bindings, must be 1;
57 - the "phy" clock is required by the phy module, used as a gate
59 PHY module
64 The first phandle argument in the PHY specifier identifies the PHY, its
71 Exynos3250 has only USB device phy available as phy 0.
80 usbphy: phy@125b0000 {
81 compatible = "samsung,exynos4x12-usb2-phy";
84 clock-names = "phy", "ref";
85 #phy-cells = <1>;
90 Then the PHY can be used in other nodes such as:
92 phy-consumer@12340000 {
94 phy-names = "phy";
97 Refer to DT bindings documentation of particular PHY consumer devices for more
100 Samsung SATA PHY Controller
103 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
104 Each SATA PHY controller should have its own node.
107 - compatible : compatible list, contains "samsung,exynos5250-sata-phy"
108 - reg : offset and length of the SATA PHY register set;
109 - #phy-cells : must be zero
116 sata_phy: sata-phy@12170000 {
117 compatible = "samsung,exynos5250-sata-phy";
121 #phy-cells = <0>;
135 sata_phy_i2c:sata-phy@38 {
140 Samsung Exynos5 SoC series USB DRD PHY controller
145 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
146 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
147 - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC.
148 - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
149 - reg : Register offset and length of USB DRD PHY register set;
153 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
155 - ref: PHY's reference clock (usually crystal clock), used for
156 PHY operations, associated by phy name. It is used to
161 - phy_pipe: for PIPE3 phy
162 - phy_utmi: for UTMI+ phy
166 - #phy-cells : from the generic PHY bindings, must be 1;
168 For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
169 compatible PHYs, the second cell in the PHY specifier identifies the
170 PHY id, which is interpreted as follows:
171 0 - UTMI+ type phy,
172 1 - PIPE3 type phy,
176 compatible = "samsung,exynos5250-usbdrd-phy";
179 clock-names = "phy", "ref";
181 #phy-cells = <1>;
184 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
194 Samsung Exynos SoC series PCIe PHY controller
197 - compatible : Should be set to "samsung,exynos5440-pcie-phy"
198 - #phy-cells : Must be zero
199 - reg : a register used by phy driver.
200 - First is for phy register, second is for block register.
201 - reg-names : Must be set to "phy" and "block".
204 pcie_phy0: pcie-phy@270000 {
205 #phy-cells = <0>;
206 compatible = "samsung,exynos5440-pcie-phy";
208 reg-names = "phy", "block";