Lines Matching +full:usb2 +full:- +full:phy
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 2.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - const: renesas,usb2-phy-r8a77470 # RZ/G1C
18 - items:
19 - enum:
20 - renesas,usb2-phy-r7s9210 # RZ/A2
21 - renesas,usb2-phy-r8a774a1 # RZ/G2M
22 - renesas,usb2-phy-r8a774b1 # RZ/G2N
23 - renesas,usb2-phy-r8a774c0 # RZ/G2E
24 - renesas,usb2-phy-r8a774e1 # RZ/G2H
25 - renesas,usb2-phy-r8a7795 # R-Car H3
26 - renesas,usb2-phy-r8a7796 # R-Car M3-W
27 - renesas,usb2-phy-r8a77961 # R-Car M3-W+
28 - renesas,usb2-phy-r8a77965 # R-Car M3-N
29 - renesas,usb2-phy-r8a77990 # R-Car E3
30 - renesas,usb2-phy-r8a77995 # R-Car D3
31 - const: renesas,rcar-gen3-usb2-phy
40 clock-names:
44 - const: fck
45 - const: usb_x1
47 '#phy-cells':
50 The phandle's argument in the PHY specifier is the INT_STATUS bit of
52 - 1 = USBH_INTA (OHCI)
53 - 2 = USBH_INTB (EHCI)
54 - 3 = UCOM_INT (OTG and BC)
59 power-domains:
66 - description: reset of USB 2.0 host side
67 - description: reset of USB 2.0 peripheral side
69 vbus-supply:
72 will be managed during the PHY power on/off sequence.
74 renesas,no-otg-pins:
86 - renesas,usb2-phy-r7s9210
89 - clock-names
92 - compatible
93 - reg
94 - clocks
95 - '#phy-cells'
100 - |
101 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
102 #include <dt-bindings/interrupt-controller/arm-gic.h>
103 #include <dt-bindings/power/r8a7795-sysc.h>
105 usb-phy@ee080200 {
106 compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
110 #phy-cells = <1>;
113 usb-phy@ee0a0200 {
114 compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
117 #phy-cells = <1>;