Lines Matching +full:usb +full:- +full:port +full:- +full:id

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Heiko Stuebner <heiko@sntech.de>
15       - rockchip,px30-usb2phy
16       - rockchip,rk3228-usb2phy
17       - rockchip,rk3328-usb2phy
18       - rockchip,rk3366-usb2phy
19       - rockchip,rk3399-usb2phy
20       - rockchip,rv1108-usb2phy
25   clock-output-names:
27       The usb 480m output clock name.
29   "#clock-cells":
32   "#phy-cells":
38   clock-names:
41   assigned-clocks:
43       Phandle of the usb 480m clock.
45   assigned-clock-parents:
47       Parent of the usb 480m clock.
48       Select between usb-phy output 480m and xin24m.
49       Refer to clk/clock-bindings.txt for generic clock consumer properties.
58       Phandle to the syscon managing the 'usb general register files'.
59       When set the driver will request its phandle as one companion-grf
62   host-port:
67       "#phy-cells":
73       interrupt-names:
76       phy-supply:
79           See ./phy-bindings.txt for details.
82       - "#phy-cells"
83       - interrupts
84       - interrupt-names
86   otg-port:
91       "#phy-cells":
98       interrupt-names:
100           - const: linestate
101           - const: otg-mux
102           - items:
103               - const: otg-bvalid
104               - const: otg-id
105               - const: linestate
107       phy-supply:
110           See ./phy-bindings.txt for details.
113       - "#phy-cells"
114       - interrupts
115       - interrupt-names
118   - compatible
119   - reg
120   - clock-output-names
121   - "#clock-cells"
122   - "#phy-cells"
123   - host-port
124   - otg-port
129   - |
130     #include <dt-bindings/clock/rk3399-cru.h>
131     #include <dt-bindings/interrupt-controller/arm-gic.h>
132     #include <dt-bindings/interrupt-controller/irq.h>
133     u2phy0: usb2-phy@e450 {
134       compatible = "rockchip,rk3399-usb2phy";
137       clock-names = "phyclk";
138       clock-output-names = "clk_usbphy0_480m";
139       #clock-cells = <0>;
140       #phy-cells = <0>;
142       u2phy0_host: host-port {
143         #phy-cells = <0>;
145         interrupt-names = "linestate";
148       u2phy0_otg: otg-port {
149         #phy-cells = <0>;
153         interrupt-names = "otg-bvalid", "otg-id", "linestate";