Lines Matching +full:phy +full:- +full:cadence +full:- +full:sierra

1 Cadence Sierra PHY
2 -----------------------
5 - compatible:	Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 		Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets:	Must contain an entry for each in reset-names.
9 - reset-names:	Must include "sierra_reset" and "sierra_apb".
10 		"sierra_reset" must control the reset line to the PHY.
11 		"sierra_apb" must control the reset line to the APB PHY
13 - reg:		register range for the PHY.
14 - #address-cells: Must be 1
15 - #size-cells:	Must be 0
18 - clocks:		Must contain an entry in clock-names.
19 			See ../clocks/clock-bindings.txt for details.
20 - clock-names:		Must contain "cmn_refclk_dig_div" and
23 - cdns,autoconf:	A boolean property whose presence indicates that the
24 			PHY registers will be configured by hardware. If not
25 			present, all sub-node optional properties must be
28 Sub-nodes:
29   Each group of PHY lanes with a single master lane should be represented as
30   a sub-node. Note that the actual configuration of each lane is determined by
33 Sub-node required properties:
34 - #phy-cells:	Generic PHY binding; must be 0.
35 - reg:		The master lane number.  This is the lowest numbered lane
37 - resets:	Must contain one entry which controls the reset line for the
38 		master lane of the sub-node.
41 Sub-node optional properties:
42 - cdns,num-lanes:	Number of lanes in this group.  From 1 to 4.  The
44 - cdns,phy-type:	Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
48 	pcie_phy4: pcie-phy@fd240000 {
49 		compatible = "cdns,sierra-phy-t0";
52 		reset-names = "sierra_reset", "sierra_apb";
54 		clock-names = "phy_clk";
55 		#address-cells = <1>;
56 		#size-cells = <0>;
57 		pcie0_phy0: pcie-phy@0 {
60 				cdns,num-lanes = <2>;
61 				#phy-cells = <0>;
62 				cdns,phy-type = <PHY_TYPE_PCIE>;
64 		pcie0_phy1: pcie-phy@2 {
67 				cdns,num-lanes = <1>;
68 				#phy-cells = <0>;
69 				cdns,phy-type = <PHY_TYPE_PCIE>;