Lines Matching +full:usb2 +full:- +full:phy
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
35 - compatible: Must be:
36 - Tegra124: "nvidia,tegra124-xusb-padctl"
37 - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38 - Tegra210: "nvidia,tegra210-xusb-padctl"
39 - Tegra186: "nvidia,tegra186-xusb-padctl"
40 - Tegra194: "nvidia,tegra194-xusb-padctl"
41 - reg: Physical base address and length of the controller's registers.
42 - resets: Must contain an entry for each entry in reset-names.
43 - reset-names: Must include the following entries:
44 - "padctl"
47 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
48 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
49 - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
50 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
53 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
54 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
55 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
56 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
59 - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
61 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
63 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
64 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
67 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
69 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
82 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
85 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
89 ---------
92 - clocks: Must contain an entry for each entry in clock-names.
93 - clock-names: Must contain the following entries:
94 - "trk": phandle and specifier referring to the USB2 tracking clock
97 ---------
100 - clocks: Must contain an entry for each entry in clock-names.
101 - clock-names: Must contain the following entries:
102 - "trk": phandle and specifier referring to the HSIC tracking clock
105 ---------
108 - clocks: Must contain an entry for each entry in clock-names.
109 - clock-names: Must contain the following entries:
110 - "pll": phandle and specifier referring to the PLLE
111 - resets: Must contain an entry for each entry in reset-names.
112 - reset-names: Must contain the following entries:
113 - "phy": reset for the PCIe UPHY block
116 ---------
119 - resets: Must contain an entry for each entry in reset-names.
120 - reset-names: Must contain the following entries:
121 - "phy": reset for the SATA UPHY block
124 PHY nodes:
131 --------------------
132 - status: Defines the operation status of the PHY. Valid values are:
133 - "disabled": the PHY is disabled
134 - "okay": the PHY is enabled
135 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
137 - nvidia,function: The output function of the PHY. See below for a list of
140 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
141 - usb2: usb2-0, usb2-1, usb2-2
142 - functions: "snps", "xusb", "uart"
143 - ulpi: ulpi-0
144 - functions: "snps", "xusb"
145 - hsic: hsic-0, hsic-1
146 - functions: "snps", "xusb"
147 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
148 - functions: "pcie", "usb3-ss"
149 - sata: sata-0
150 - functions: "usb3-ss", "sata"
152 For Tegra210, the list of valid PHY nodes is given below:
153 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
154 - functions: "snps", "xusb", "uart"
155 - hsic: hsic-0, hsic-1
156 - functions: "snps", "xusb"
157 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
158 - functions: "pcie-x1", "usb3-ss", "pcie-x4"
159 - sata: sata-0
160 - functions: "usb3-ss", "sata"
162 For Tegra194, the list of valid PHY nodes is given below:
163 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
164 - functions: "xusb"
165 - usb3: usb3-0, usb3-1, usb3-2, usb3-3
166 - functions: "xusb"
172 by the XUSB pad controller. Per-port configuration is only required for USB.
174 USB2 ports:
175 -----------
178 - status: Defines the operation status of the port. Valid values are:
179 - "disabled": the port is disabled
180 - "okay": the port is enabled
181 - mode: A string that determines the mode in which to run the port. Valid
183 - "host": for USB host mode
184 - "device": for USB device mode
185 - "otg": for USB OTG mode
187 Required properties for OTG/Peripheral capable USB2 ports:
188 - usb-role-switch: Boolean property to indicate that the port support OTG or
191 See usb/usb-conn-gpio.txt.
194 - nvidia,internal: A boolean property whose presence determines that a port
197 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
200 -----------
203 - status: Defines the operation status of the port. Valid values are:
204 - "disabled": the port is disabled
205 - "okay": the port is enabled
206 - nvidia,internal: A boolean property whose presence determines that a port
209 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
212 -----------
215 - status: Defines the operation status of the port. Valid values are:
216 - "disabled": the port is disabled
217 - "okay": the port is enabled
220 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
222 Super-speed USB ports:
223 ----------------------
226 - status: Defines the operation status of the port. Valid values are:
227 - "disabled": the port is disabled
228 - "okay": the port is enabled
229 - nvidia,usb2-companion: A single cell that specifies the physical port number
230 to map this super-speed USB port to. The range of valid port numbers varies
232 - 0-2: for Tegra124 and Tegra132
233 - 0-3: for Tegra210
236 - nvidia,internal: A boolean property whose presence determines that a port
240 - maximum-speed: Only for Tegra194. A string property that specifies maximum
242 - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
243 - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
247 - 3x USB2: usb2-0, usb2-1, usb2-2
248 - 1x ULPI: ulpi-0
249 - 2x HSIC: hsic-0, hsic-1
250 - 2x super-speed USB: usb3-0, usb3-1
253 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
254 - 2x HSIC: hsic-0, hsic-1
255 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
258 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
259 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
265 ----------------------
271 compatible = "nvidia,tegra124-xusb-padctl";
273 compatible = "nvidia,tegra132-xusb-padctl",
274 "nvidia,tegra124-xusb-padctl";
277 reset-names = "padctl";
280 usb2 {
284 usb2-0 {
286 #phy-cells = <0>;
289 usb2-1 {
291 #phy-cells = <0>;
294 usb2-2 {
296 #phy-cells = <0>;
305 ulpi-0 {
307 #phy-cells = <0>;
316 hsic-0 {
318 #phy-cells = <0>;
321 hsic-1 {
323 #phy-cells = <0>;
332 pcie-0 {
334 #phy-cells = <0>;
337 pcie-1 {
339 #phy-cells = <0>;
342 pcie-2 {
344 #phy-cells = <0>;
347 pcie-3 {
349 #phy-cells = <0>;
352 pcie-4 {
354 #phy-cells = <0>;
363 sata-0 {
365 #phy-cells = <0>;
372 usb2-0 {
376 usb2-1 {
380 usb2-2 {
384 ulpi-0 {
388 hsic-0 {
392 hsic-1 {
396 usb3-0 {
400 usb3-1 {
412 usb2 {
416 usb2-0 {
421 usb2-1 {
426 usb2-2 {
437 pcie-0 {
438 nvidia,function = "usb3-ss";
442 pcie-2 {
447 pcie-4 {
458 sata-0 {
468 usb2-0 {
474 usb2-1 {
480 usb2-2 {
484 vbus-supply = <&vdd_usb3_vbus>;
487 usb3-0 {
495 ---------
500 compatible = "nvidia,tegra210-xusb-padctl";
503 reset-names = "padctl";
508 usb2 {
510 clock-names = "trk";
514 usb2-0 {
516 #phy-cells = <0>;
519 usb2-1 {
521 #phy-cells = <0>;
524 usb2-2 {
526 #phy-cells = <0>;
529 usb2-3 {
531 #phy-cells = <0>;
538 clock-names = "trk";
542 hsic-0 {
544 #phy-cells = <0>;
547 hsic-1 {
549 #phy-cells = <0>;
556 clock-names = "pll";
558 reset-names = "phy";
562 pcie-0 {
564 #phy-cells = <0>;
567 pcie-1 {
569 #phy-cells = <0>;
572 pcie-2 {
574 #phy-cells = <0>;
577 pcie-3 {
579 #phy-cells = <0>;
582 pcie-4 {
584 #phy-cells = <0>;
587 pcie-5 {
589 #phy-cells = <0>;
592 pcie-6 {
594 #phy-cells = <0>;
601 clock-names = "pll";
603 reset-names = "phy";
607 sata-0 {
609 #phy-cells = <0>;
616 usb2-0 {
620 usb2-1 {
624 usb2-2 {
628 usb2-3 {
632 hsic-0 {
636 hsic-1 {
640 usb3-0 {
644 usb3-1 {
648 usb3-2 {
652 usb3-3 {
664 usb2 {
668 usb2-0 {
673 usb2-1 {
678 usb2-2 {
683 usb2-3 {
694 pcie-0 {
695 nvidia,function = "pcie-x1";
699 pcie-1 {
700 nvidia,function = "pcie-x4";
704 pcie-2 {
705 nvidia,function = "pcie-x4";
709 pcie-3 {
710 nvidia,function = "pcie-x4";
714 pcie-4 {
715 nvidia,function = "pcie-x4";
719 pcie-5 {
720 nvidia,function = "usb3-ss";
724 pcie-6 {
725 nvidia,function = "usb3-ss";
735 sata-0 {
744 usb2-0 {
749 usb2-1 {
751 vbus-supply = <&vdd_5v0_rtl>;
755 usb2-2 {
757 vbus-supply = <&vdd_usb_vbus>;
761 usb2-3 {
766 usb3-0 {
768 nvidia,lanes = "pcie-6";
772 usb3-1 {
774 nvidia,lanes = "pcie-5";