Lines Matching +full:sun8i +full:- +full:r40 +full:- +full:usb +full:- +full:phy
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner R40 USB PHY Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-r40-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
24 - description: PHY PMU1 registers
25 - description: PHY PMU2 registers
27 reg-names:
29 - const: phy_ctrl
30 - const: pmu0
31 - const: pmu1
32 - const: pmu2
36 - description: USB OTG PHY bus clock
37 - description: USB Host 0 PHY bus clock
38 - description: USB Host 1 PHY bus clock
40 clock-names:
42 - const: usb0_phy
43 - const: usb1_phy
44 - const: usb2_phy
48 - description: USB OTG reset
49 - description: USB Host 1 Controller reset
50 - description: USB Host 2 Controller reset
52 reset-names:
54 - const: usb0_reset
55 - const: usb1_reset
56 - const: usb2_reset
58 usb0_id_det-gpios:
59 description: GPIO to the USB OTG ID pin
61 usb0_vbus_det-gpios:
62 description: GPIO to the USB OTG VBUS detect pin
64 usb0_vbus_power-supply:
65 description: Power supply to detect the USB OTG VBUS
67 usb0_vbus-supply:
68 description: Regulator controlling USB OTG VBUS
70 usb1_vbus-supply:
73 usb2_vbus-supply:
77 - "#phy-cells"
78 - compatible
79 - clocks
80 - clock-names
81 - reg
82 - reg-names
83 - resets
84 - reset-names
89 - |
90 #include <dt-bindings/gpio/gpio.h>
91 #include <dt-bindings/clock/sun8i-r40-ccu.h>
92 #include <dt-bindings/reset/sun8i-r40-ccu.h>
94 phy@1c13400 {
95 #phy-cells = <1>;
96 compatible = "allwinner,sun8i-r40-usb-phy";
101 reg-names = "phy_ctrl",
108 clock-names = "usb0_phy",
114 reset-names = "usb0_reset",
117 usb1_vbus-supply = <®_vcc5v0>;
118 usb2_vbus-supply = <®_vcc5v0>;