Lines Matching +full:sun8i +full:- +full:a23 +full:- +full:a33 +full:- +full:ccu
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A23 USB PHY Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a23-usb-phy
20 - allwinner,sun8i-a33-usb-phy
24 - description: PHY Control registers
25 - description: PHY PMU1 registers
27 reg-names:
29 - const: phy_ctrl
30 - const: pmu1
34 - description: USB OTG PHY bus clock
35 - description: USB Host 0 PHY bus clock
37 clock-names:
39 - const: usb0_phy
40 - const: usb1_phy
44 - description: USB OTG reset
45 - description: USB Host 1 Controller reset
47 reset-names:
49 - const: usb0_reset
50 - const: usb1_reset
52 usb0_id_det-gpios:
55 usb0_vbus_det-gpios:
58 usb0_vbus_power-supply:
61 usb0_vbus-supply:
64 usb1_vbus-supply:
68 - "#phy-cells"
69 - compatible
70 - clocks
71 - clock-names
72 - reg
73 - reg-names
74 - resets
75 - reset-names
80 - |
81 #include <dt-bindings/gpio/gpio.h>
82 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
83 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
86 #phy-cells = <1>;
87 compatible = "allwinner,sun8i-a23-usb-phy";
89 reg-names = "phy_ctrl", "pmu1";
90 clocks = <&ccu CLK_USB_PHY0>,
91 <&ccu CLK_USB_PHY1>;
92 clock-names = "usb0_phy",
94 resets = <&ccu RST_USB_PHY0>,
95 <&ccu RST_USB_PHY1>;
96 reset-names = "usb0_reset",
98 usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
99 usb0_vbus_power-supply = <&usb_power_supply>;
100 usb0_vbus-supply = <®_drivevbus>;
101 usb1_vbus-supply = <®_usb1_vbus>;