Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:ccu
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 USB PHY Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun4i-a10-usb-phy
20 - allwinner,sun7i-a20-usb-phy
24 - description: PHY Control registers
25 - description: PHY PMU1 registers
26 - description: PHY PMU2 registers
28 reg-names:
30 - const: phy_ctrl
31 - const: pmu1
32 - const: pmu2
38 clock-names:
43 - description: USB OTG reset
44 - description: USB Host 1 Controller reset
45 - description: USB Host 2 Controller reset
47 reset-names:
49 - const: usb0_reset
50 - const: usb1_reset
51 - const: usb2_reset
53 usb0_id_det-gpios:
56 usb0_vbus_det-gpios:
59 usb0_vbus_power-supply:
62 usb0_vbus-supply:
65 usb1_vbus-supply:
68 usb2_vbus-supply:
72 - "#phy-cells"
73 - compatible
74 - clocks
75 - clock-names
76 - reg
77 - reg-names
78 - resets
79 - reset-names
84 - |
85 #include <dt-bindings/gpio/gpio.h>
86 #include <dt-bindings/clock/sun4i-a10-ccu.h>
87 #include <dt-bindings/reset/sun4i-a10-ccu.h>
90 #phy-cells = <1>;
91 compatible = "allwinner,sun4i-a10-usb-phy";
93 reg-names = "phy_ctrl", "pmu1", "pmu2";
94 clocks = <&ccu CLK_USB_PHY>;
95 clock-names = "usb_phy";
96 resets = <&ccu RST_USB_PHY0>,
97 <&ccu RST_USB_PHY1>,
98 <&ccu RST_USB_PHY2>;
99 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
100 usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>;
101 usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
102 usb0_vbus-supply = <®_usb0_vbus>;
103 usb1_vbus-supply = <®_usb1_vbus>;
104 usb2_vbus-supply = <®_usb2_vbus>;