Lines Matching +full:max +full:- +full:link +full:- +full:speed
3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
22 If present this property specifies PCI gen for link capability. Host
24 unsupported link speed, for instance, trying to do training for
25 unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
27 - reset-gpios:
30 - supports-clkreq:
34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
36 PCI-PCI Bridge properties
37 -------------------------
46 - reg:
47 Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
48 document, it is a five-cell address encoded as (phys.hi phys.mid
56 number of a root port is the first number in the bus-range property,
60 above this port, then phys.hi contains the 8-bit function number as
63 OS is ARI-aware.
67 - external-facing:
68 When present, the port is external-facing. All bridges and endpoints
77 compatible = "pci-host-ecam-generic";
80 /* Root port 00:01.0 is external-facing */
82 external-facing;