Lines Matching +full:3 +full:- +full:port
5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
15 - ranges: ranges describing the MMIO registers to control the PCIe
18 - msi-parent: Link to the hardware entity that serves as the Message
27 * r is a 32-bits value that gives the offset of the MMIO
31 * s is a 32-bits value that give the size of this MMIO
57 In addition, the device tree node must have sub-nodes describing each
60 - reg: used only for interrupt mapping, so only the first four bytes
62 - assigned-addresses: reference to the MMIO registers used to control
64 - clocks: the clock associated to this PCIe interface
65 - marvell,pcie-port: the physical PCIe port number
66 - status: either "disabled" or "okay"
67 - device_type, set to "pci"
68 - #address-cells, set to <3>
69 - #size-cells, set to <2>
70 - #interrupt-cells, set to <1>
71 - ranges, translating the MBus windows ranges of the parent node into
73 - interrupt-map-mask and interrupt-map, standard PCI properties to
77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
80 - reset-gpios: optional GPIO to PERST#
81 - reset-delay-us: delay in us to wait after reset de-assertion, if not
86 pcie-controller {
87 compatible = "marvell,armada-xp-pcie";
90 #address-cells = <3>;
91 #size-cells = <2>;
93 bus-range = <0x00 0xff>;
94 msi-parent = <&mpic>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
99 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
100 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
101 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
102 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
103 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
104 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
105 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
106 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
107 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
108 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
109 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
110 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
111 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
112 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
113 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
114 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
116 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
117 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
118 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
119 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
120 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
121 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
122 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
123 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
125 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
126 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
128 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
129 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
133 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 58>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <0>;
144 /* low-active PERST# reset on GPIO 25 */
145 reset-gpios = <&gpio0 25 1>;
147 reset-delay-us = <20000>;
153 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 #interrupt-cells = <1>;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 59>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <1>;
167 pcie@3,0 {
169 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
171 #address-cells = <3>;
172 #size-cells = <2>;
173 #interrupt-cells = <1>;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 60>;
178 marvell,pcie-port = <0>;
179 marvell,pcie-lane = <2>;
185 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
187 #address-cells = <3>;
188 #size-cells = <2>;
189 #interrupt-cells = <1>;
192 interrupt-map-mask = <0 0 0 0>;
193 interrupt-map = <0 0 0 0 &mpic 61>;
194 marvell,pcie-port = <0>;
195 marvell,pcie-lane = <3>;
201 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
203 #address-cells = <3>;
204 #size-cells = <2>;
205 #interrupt-cells = <1>;
208 interrupt-map-mask = <0 0 0 0>;
209 interrupt-map = <0 0 0 0 &mpic 62>;
210 marvell,pcie-port = <1>;
211 marvell,pcie-lane = <0>;
217 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
219 #address-cells = <3>;
220 #size-cells = <2>;
221 #interrupt-cells = <1>;
224 interrupt-map-mask = <0 0 0 0>;
225 interrupt-map = <0 0 0 0 &mpic 63>;
226 marvell,pcie-port = <1>;
227 marvell,pcie-lane = <1>;
233 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
235 #address-cells = <3>;
236 #size-cells = <2>;
237 #interrupt-cells = <1>;
240 interrupt-map-mask = <0 0 0 0>;
241 interrupt-map = <0 0 0 0 &mpic 64>;
242 marvell,pcie-port = <1>;
243 marvell,pcie-lane = <2>;
249 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
251 #address-cells = <3>;
252 #size-cells = <2>;
253 #interrupt-cells = <1>;
256 interrupt-map-mask = <0 0 0 0>;
257 interrupt-map = <0 0 0 0 &mpic 65>;
258 marvell,pcie-port = <1>;
259 marvell,pcie-lane = <3>;
265 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
267 #address-cells = <3>;
268 #size-cells = <2>;
269 #interrupt-cells = <1>;
272 interrupt-map-mask = <0 0 0 0>;
273 interrupt-map = <0 0 0 0 &mpic 99>;
274 marvell,pcie-port = <2>;
275 marvell,pcie-lane = <0>;
281 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
283 #address-cells = <3>;
284 #size-cells = <2>;
285 #interrupt-cells = <1>;
288 interrupt-map-mask = <0 0 0 0>;
289 interrupt-map = <0 0 0 0 &mpic 103>;
290 marvell,pcie-port = <3>;
291 marvell,pcie-lane = <0>;