Lines Matching +full:0 +full:x1a000000
31 where N starting from 0 to one less than the number of root ports.
76 reg = <0 0x1a000000 0 0x1000>;
84 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
85 <0 0x1a142000 0 0x1000>, /* Port0 registers */
86 <0 0x1a143000 0 0x1000>, /* Port1 registers */
87 <0 0x1a144000 0 0x1000>; /* Port2 registers */
92 interrupt-map-mask = <0xf800 0 0 0>;
93 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
94 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
95 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
109 bus-range = <0x00 0xff>;
110 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
111 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
113 pcie@0,0 {
114 reg = <0x0000 0 0 0 0>;
118 interrupt-map-mask = <0 0 0 0>;
119 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
123 pcie@1,0 {
124 reg = <0x0800 0 0 0 0>;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
133 pcie@2,0 {
134 reg = <0x1000 0 0 0 0>;
138 interrupt-map-mask = <0 0 0 0>;
139 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
149 reg = <0 0x11700000 0 0x1000>,
150 <0 0x112ff000 0 0x1000>;
163 bus-range = <0x00 0xff>;
164 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
166 pcie0: pcie@0,0 {
167 reg = <0x0000 0 0 0 0>;
172 interrupt-map-mask = <0 0 0 7>;
173 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
174 <0 0 0 2 &pcie_intc0 1>,
175 <0 0 0 3 &pcie_intc0 2>,
176 <0 0 0 4 &pcie_intc0 3>;
179 #address-cells = <0>;
184 pcie1: pcie@1,0 {
185 reg = <0x0800 0 0 0 0>;
190 interrupt-map-mask = <0 0 0 7>;
191 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
192 <0 0 0 2 &pcie_intc1 1>,
193 <0 0 0 3 &pcie_intc1 2>,
194 <0 0 0 4 &pcie_intc1 3>;
197 #address-cells = <0>;
208 reg = <0 0x1a140000 0 0x1000>,
209 <0 0x1a143000 0 0x1000>,
210 <0 0x1a145000 0 0x1000>;
234 bus-range = <0x00 0xff>;
235 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
237 pcie0: pcie@0,0 {
238 reg = <0x0000 0 0 0 0>;
243 interrupt-map-mask = <0 0 0 7>;
244 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
245 <0 0 0 2 &pcie_intc0 1>,
246 <0 0 0 3 &pcie_intc0 2>,
247 <0 0 0 4 &pcie_intc0 3>;
250 #address-cells = <0>;
255 pcie1: pcie@1,0 {
256 reg = <0x0800 0 0 0 0>;
261 interrupt-map-mask = <0 0 0 7>;
262 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
263 <0 0 0 2 &pcie_intc1 1>,
264 <0 0 0 3 &pcie_intc1 2>,
265 <0 0 0 4 &pcie_intc1 3>;
268 #address-cells = <0>;