Lines Matching +full:ethernet +full:- +full:phy
1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
5 provides connectivity to an external ethernet PHY supporting different
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
27 instead, and only the Ethernet core interrupt is optionally
29 - phy-handle : Should point to the external phy device.
30 See ethernet.txt file in the same directory.
31 - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
34 - phy-mode : See ethernet.txt
35 - xlnx,phy-type : Deprecated, do not use, but still accepted in preference
36 to phy-mode.
37 - xlnx,txcsum : 0 or empty for disabling TX checksum offload,
40 - xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
41 - clocks : AXI bus clock for the device. Refer to common clock bindings.
43 auto-detected from the CPU clock (but only on platforms where
44 this is possible). New device trees should specify this - the
46 - axistream-connected: Reference to another node which contains the resources
48 If this is specified, the DMA-related resources from that
51 - mdio : Child node for MDIO bus. Must be defined if PHY access is
53 unless the PHY is accessed through a different bus).
56 axi_ethernet_eth: ethernet@40c00000 {
57 compatible = "xlnx,axi-ethernet-1.00.a";
59 interrupt-parent = <µblaze_0_axi_intc>;
62 phy-mode = "mii";
67 phy-handle = <&phy0>;
69 #address-cells = <1>;
70 #size-cells = <0>;
71 phy0: phy@0 {
72 device_type = "ethernet-phy";