Lines Matching +full:cpsw +full:- +full:mdio
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
18 Input/Output (MDIO) interface for physical layer device (PHY) management,
25 Peripheral Root Complex (UDMA-P) controller.
47 "#address-cells": true
48 "#size-cells": true
52 - const: ti,am654-cpsw-nuss
53 - const: ti,j721e-cpsw-nuss
60 reg-names:
62 - const: cpsw_nuss
66 dma-coherent: true
71 clock-names:
73 - const: fck
75 power-domains:
81 dma-names:
83 - const: tx0
84 - const: tx1
85 - const: tx2
86 - const: tx3
87 - const: tx4
88 - const: tx5
89 - const: tx6
90 - const: tx7
91 - const: rx
93 ethernet-ports:
96 '#address-cells':
98 '#size-cells':
106 $ref: ethernet-controller.yaml#
111 - const: 1
112 description: CPSW port number
116 description: phandle on phy-gmii-sel PHY
121 ti,mac-only:
124 Specifies the port works in mac-only mode.
126 ti,syscon-efuse:
127 $ref: /schemas/types.yaml#definitions/phandle-array
133 - reg
134 - phys
139 "^mdio@[0-9a-f]+$":
141 $ref: "ti,davinci-mdio.yaml#"
144 CPSW MDIO bus.
146 "^cpts@[0-9a-f]+":
148 $ref: "ti,k3-am654-cpts.yaml#"
150 CPSW Common Platform Time Sync (CPTS) module.
153 - compatible
154 - reg
155 - reg-names
156 - ranges
157 - clocks
158 - clock-names
159 - power-domains
160 - dmas
161 - dma-names
162 - '#address-cells'
163 - '#size-cells'
168 - |
169 #include <dt-bindings/pinctrl/k3.h>
170 #include <dt-bindings/soc/ti,sci_pm_domain.h>
171 #include <dt-bindings/net/ti-dp83867.h>
172 #include <dt-bindings/interrupt-controller/irq.h>
173 #include <dt-bindings/interrupt-controller/arm-gic.h>
176 #address-cells = <2>;
177 #size-cells = <2>;
180 compatible = "ti,am654-cpsw-nuss";
181 #address-cells = <2>;
182 #size-cells = <2>;
184 reg-names = "cpsw_nuss";
186 dma-coherent;
188 clock-names = "fck";
189 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
202 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
205 ethernet-ports {
206 #address-cells = <1>;
207 #size-cells = <0>;
211 ti,mac-only;
213 ti,syscon-efuse = <&mcu_conf 0x200>;
216 phy-mode = "rgmii-rxid";
217 phy-handle = <&phy0>;
221 davinci_mdio: mdio@f00 {
222 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
224 #address-cells = <1>;
225 #size-cells = <0>;
227 clock-names = "fck";
230 phy0: ethernet-phy@0 {
232 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
233 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
239 compatible = "ti,am65-cpts";
242 clock-names = "cpts";
243 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
244 interrupt-names = "cpts";
245 ti,cpts-ext-ts-inputs = <4>;
246 ti,cpts-periodic-outputs = <2>;