Lines Matching +full:cpsw +full:- +full:mdio
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
18 the management data input output (MDIO) for physical layer device (PHY)
24 - const: ti,cpsw-switch
25 - items:
26 - const: ti,am335x-cpsw-switch
27 - const: ti,cpsw-switch
28 - items:
29 - const: ti,am4372-cpsw-switch
30 - const: ti,cpsw-switch
31 - items:
32 - const: ti,dra7-cpsw-switch
33 - const: ti,cpsw-switch
38 The physical base address and size of full the CPSW module IO range
40 '#address-cells':
43 '#size-cells':
50 description: CPSW functional clock
52 clock-names:
54 - const: fck
58 - description: RX_THRESH interrupt
59 - description: RX interrupt
60 - description: TX interrupt
61 - description: MISC interrupt
63 interrupt-names:
65 - const: "rx_thresh"
66 - const: "rx"
67 - const: "tx"
68 - const: "misc"
70 pinctrl-names: true
78 ethernet-ports:
81 '#address-cells':
83 '#size-cells':
87 "^port@[0-9]+$":
89 description: CPSW external ports
92 - $ref: ethernet-controller.yaml#
97 - enum: [1, 2]
98 description: CPSW port number
102 description: phandle on phy-gmii-sel PHY
107 ti,dual-emac-pvid:
113 ports. Default value - CPSW port number.
116 - reg
117 - phys
129 clock-names:
131 - const: cpts
146 - clocks
147 - clock-names
150 "^mdio@":
153 CPSW MDIO bus.
154 $ref: "ti,davinci-mdio.yaml#"
158 - compatible
159 - reg
160 - ranges
161 - clocks
162 - clock-names
163 - interrupts
164 - interrupt-names
165 - '#address-cells'
166 - '#size-cells'
171 - |
172 #include <dt-bindings/interrupt-controller/irq.h>
173 #include <dt-bindings/interrupt-controller/arm-gic.h>
174 #include <dt-bindings/clock/dra7.h>
177 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
181 clock-names = "fck";
182 #address-cells = <1>;
183 #size-cells = <1>;
190 interrupt-names = "rx_thresh", "rx", "tx", "misc";
192 ethernet-ports {
193 #address-cells = <1>;
194 #size-cells = <0>;
199 mac-address = [ 00 00 00 00 00 00 ];
201 phy-handle = <ðphy0_sw>;
202 phy-mode = "rgmii";
203 ti,dual-emac-pvid = <1>;
209 mac-address = [ 00 00 00 00 00 00 ];
211 phy-handle = <ðphy1_sw>;
212 phy-mode = "rgmii";
213 ti,dual-emac-pvid = <2>;
217 davinci_mdio_sw: mdio@1000 {
218 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
221 clock-names = "fck";
222 #address-cells = <1>;
223 #size-cells = <0>;
226 ethphy0_sw: ethernet-phy@0 {
230 ethphy1_sw: ethernet-phy@1 {
237 clock-names = "cpts";