Lines Matching +full:soc +full:- +full:glue
1 STMicroelectronics SoC DWMAC glue layer controller
5 and what is needed on STi platforms to program the stmmac glue logic.
10 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
11 "st,stih407-dwmac", "st,stid127-dwmac".
12 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 encompases the glue register, and the offset of the control register.
14 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 register available on STiH407 SoC.
16 - pinctrl-0: pin-control for all the MII mode supported.
19 - resets : phandle pointing to the system reset controller with correct
21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
23 - st,tx-retime-src: This specifies which clk is wired up to the mac for
27 - sti-ethclk: this is the phy clock.
28 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
30 - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
37 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
39 reg-names = "stmmaceth";
44 reset-names = "stmmaceth";
49 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
52 snps,mixed-burst;
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_rgmii1>;
57 clock-names = "stmmaceth", "sti-ethclk";