Lines Matching +full:phy +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
23 - qca,ar7242-eth # Atheros AR7242
24 - qca,ar9130-eth # Atheros AR9130
25 - qca,ar9330-eth # Atheros AR9330
26 - qca,ar9340-eth # Atheros AR9340
27 - qca,qca9530-eth # Qualcomm Atheros QCA9530
28 - qca,qca9550-eth # Qualcomm Atheros QCA9550
29 - qca,qca9560-eth # Qualcomm Atheros QCA9560
37 '#address-cells':
41 '#size-cells':
47 - description: MAC main clock
48 - description: MDIO clock
50 clock-names:
52 - const: eth
53 - const: mdio
57 - description: MAC reset
58 - description: MDIO reset
60 reset-names:
62 - const: mac
63 - const: mdio
66 - compatible
67 - reg
68 - interrupts
69 - phy-mode
70 - clocks
71 - clock-names
72 - resets
73 - reset-names
79 - |
81 compatible = "qca,ar9330-eth";
85 reset-names = "mac", "mdio";
87 clock-names = "eth", "mdio";
89 phy-mode = "mii";
90 phy-handle = <&phy_port4>;
94 compatible = "qca,ar9330-eth";
98 reset-names = "mac", "mdio";
100 clock-names = "eth", "mdio";
102 phy-mode = "gmii";
106 fixed-link {
108 full-duplex;
112 #address-cells = <1>;
113 #size-cells = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
119 compatible = "qca,ar9331-switch";
122 reset-names = "switch";
124 interrupt-parent = <&miscintc>;
127 interrupt-controller;
128 #interrupt-cells = <1>;
131 #address-cells = <1>;
132 #size-cells = <0>;
139 phy-mode = "gmii";
141 fixed-link {
143 full-duplex;
149 phy-handle = <&phy_port0>;
150 phy-mode = "internal";
157 phy-handle = <&phy_port1>;
158 phy-mode = "internal";
165 phy-handle = <&phy_port2>;
166 phy-mode = "internal";
173 phy-handle = <&phy_port3>;
174 phy-mode = "internal";
181 #address-cells = <1>;
182 #size-cells = <0>;
184 interrupt-parent = <&switch10>;
186 phy_port0: phy@0 {
192 phy_port1: phy@1 {
198 phy_port2: phy@2 {
204 phy_port3: phy@3 {
210 phy_port4: phy@4 {