Lines Matching +full:0 +full:- +full:3
8 - compatible : mdio-mux-gpio.
9 - gpios : GPIO specifiers for each GPIO line. One or more must be specified.
16 compatible = "cavium,octeon-3860-mdio";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 reg = <0x11800 0x00001900 0x0 0x40>;
23 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
24 pair of GPIO lines. Child busses 2 and 3 populated with 4
27 mdio-mux {
28 compatible = "mdio-mux-gpio";
29 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
30 mdio-parent-bus = <&smi1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 #address-cells = <1>;
37 #size-cells = <0>;
39 phy11: ethernet-phy@1 {
41 marvell,reg-init = <3 0x10 0 0x5777>,
42 <3 0x11 0 0x00aa>,
43 <3 0x12 0 0x4105>,
44 <3 0x13 0 0x0a60>;
45 interrupt-parent = <&gpio>;
48 phy12: ethernet-phy@2 {
50 marvell,reg-init = <3 0x10 0 0x5777>,
51 <3 0x11 0 0x00aa>,
52 <3 0x12 0 0x4105>,
53 <3 0x13 0 0x0a60>;
54 interrupt-parent = <&gpio>;
57 phy13: ethernet-phy@3 {
58 reg = <3>;
59 marvell,reg-init = <3 0x10 0 0x5777>,
60 <3 0x11 0 0x00aa>,
61 <3 0x12 0 0x4105>,
62 <3 0x13 0 0x0a60>;
63 interrupt-parent = <&gpio>;
66 phy14: ethernet-phy@4 {
68 marvell,reg-init = <3 0x10 0 0x5777>,
69 <3 0x11 0 0x00aa>,
70 <3 0x12 0 0x4105>,
71 <3 0x13 0 0x0a60>;
72 interrupt-parent = <&gpio>;
77 mdio@3 {
78 reg = <3>;
79 #address-cells = <1>;
80 #size-cells = <0>;
82 phy21: ethernet-phy@1 {
84 marvell,reg-init = <3 0x10 0 0x5777>,
85 <3 0x11 0 0x00aa>,
86 <3 0x12 0 0x4105>,
87 <3 0x13 0 0x0a60>;
88 interrupt-parent = <&gpio>;
91 phy22: ethernet-phy@2 {
93 marvell,reg-init = <3 0x10 0 0x5777>,
94 <3 0x11 0 0x00aa>,
95 <3 0x12 0 0x4105>,
96 <3 0x13 0 0x0a60>;
97 interrupt-parent = <&gpio>;
100 phy23: ethernet-phy@3 {
101 reg = <3>;
102 marvell,reg-init = <3 0x10 0 0x5777>,
103 <3 0x11 0 0x00aa>,
104 <3 0x12 0 0x4105>,
105 <3 0x13 0 0x0a60>;
106 interrupt-parent = <&gpio>;
109 phy24: ethernet-phy@4 {
111 marvell,reg-init = <3 0x10 0 0x5777>,
112 <3 0x11 0 0x00aa>,
113 <3 0x12 0 0x4105>,
114 <3 0x13 0 0x0a60>;
115 interrupt-parent = <&gpio>;