Lines Matching +full:port +full:- +full:1
6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
30 - reset-names : Should be set to "mcm".
34 - reg: Port address described must be 6 for CPU port and from 0 to 5 for
36 - phy-mode: String, the following values are acceptable for port labeled
41 must be either "sgmii", "1000base-x" or "2500base-x"
43 Port 5 of mt7530 and mt7621 switch is muxed between:
44 1. GMAC5: GMAC5 can interface with another external MAC or PHY.
45 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
46 of the SOC. Used in many setups where port 0/4 becomes the WAN port.
48 GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
51 Port 5 modes/configurations:
52 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
54 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
56 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
57 It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
59 3. Port 5 is muxed to GMAC5 and can interface to an external phy.
60 Port 5 becomes an extra switch port.
61 Only works on platform where external phy TX<->RX lines are swapped.
62 Like in the Ubiquiti ER-X-SFP.
63 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
64 Currently a 2nd CPU port is not supported by DSA code.
67 1. normal: The PHY can only connect to 2nd GMAC but not to the switch
69 a ethernet port. But can't interface to the 2nd GMAC.
71 Based on the DT the port 5 mode is configured.
73 Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
74 When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
75 phy-mode must be set, see also example 2 below!
76 * mt7621: phy-mode = "rgmii-txid";
77 * mt7623: phy-mode = "rgmii";
88 #address-cells = <1>;
89 #size-cells = <0>;
92 core-supply = <&mt6323_vpa_reg>;
93 io-supply = <&mt6323_vemc3v3_reg>;
94 reset-gpios = <&pio 33 0>;
97 #address-cells = <1>;
98 #size-cells = <0>;
100 port@0 {
105 port@1 {
106 reg = <1>;
110 port@2 {
115 port@3 {
120 port@4 {
125 port@6 {
129 phy-mode = "trgmii";
130 fixed-link {
132 full-duplex;
139 Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
143 compatible = "mediatek,eth-mac";
145 phy-mode = "rgmii";
147 fixed-link {
149 full-duplex;
154 gmac1: mac@1 {
155 compatible = "mediatek,eth-mac";
156 reg = <1>;
157 phy-mode = "rgmii-txid";
158 phy-handle = <&phy4>;
161 mdio: mdio-bus {
162 #address-cells = <1>;
163 #size-cells = <0>;
166 phy4: ethernet-phy@4 {
170 mt7530: switch@1f {
172 #address-cells = <1>;
173 #size-cells = <0>;
175 pinctrl-names = "default";
179 reset-names = "mcm";
182 #address-cells = <1>;
183 #size-cells = <0>;
185 port@0 {
190 port@1 {
191 reg = <1>;
195 port@2 {
200 port@3 {
205 /* Commented out. Port 4 is handled by 2nd GMAC.
206 port@4 {
212 cpu_port0: port@6 {
216 phy-mode = "rgmii";
218 fixed-link {
220 full-duplex;
229 Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
233 compatible = "mediatek,eth-mac";
235 phy-mode = "rgmii";
237 fixed-link {
239 full-duplex;
244 mdio: mdio-bus {
245 #address-cells = <1>;
246 #size-cells = <0>;
249 ephy5: ethernet-phy@7 {
253 mt7530: switch@1f {
255 #address-cells = <1>;
256 #size-cells = <0>;
258 pinctrl-names = "default";
262 reset-names = "mcm";
265 #address-cells = <1>;
266 #size-cells = <0>;
268 port@0 {
273 port@1 {
274 reg = <1>;
278 port@2 {
283 port@3 {
288 port@4 {
293 port@5 {
296 phy-mode = "rgmii";
297 phy-handle = <&ephy5>;
300 cpu_port0: port@6 {
304 phy-mode = "rgmii";
306 fixed-link {
308 full-duplex;