Lines Matching +full:2 +full:nd

45 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
47    Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
52 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
54    In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
56 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
63 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
64    Currently a 2nd CPU port is not supported by DSA code.
67 1. normal: The PHY can only connect to 2nd GMAC but not to the switch
68 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
69    a ethernet port. But can't interface to the 2nd GMAC.
73 Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
74 When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
75 phy-mode must be set, see also example 2 below!
110 				port@2 {
111 					reg = <2>;
139 Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
178 			resets = <&rstctrl 2>;
195 				port@2 {
196 					reg = <2>;
205 /* Commented out. Port 4 is handled by 2nd GMAC.
261 			resets = <&rstctrl 2>;
278 				port@2 {
279 					reg = <2>;