Lines Matching +full:controller +full:- +full:specific
1 Renesas R-Car CAN FD controller Device Tree Bindings
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5 - compatible: Must contain one or more of the following:
6 - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
7 - "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller.
8 - "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller.
9 - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
10 - "renesas,r8a774e1-canfd" for R8A774E1 (RZ/G2H) compatible controller.
11 - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
12 - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
13 - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller.
14 - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller.
15 - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller.
16 - "renesas,r8a77990-canfd" for R8A77990 (R-Car E3) compatible controller.
17 - "renesas,r8a77995-canfd" for R8A77995 (R-Car D3) compatible controller.
20 SoC-specific version corresponding to the platform first, followed by the
21 family-specific and/or generic versions.
23 - reg: physical base address and size of the R-Car CAN FD register map.
24 - interrupts: interrupt specifiers for the Channel & Global interrupts
25 - clocks: phandles and clock specifiers for 3 clock inputs.
26 - clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
27 - pinctrl-0: pin control group to be used for this controller.
28 - pinctrl-names: must be "default".
31 The controller supports two channels and each is represented as a child node.
39 and CAN FD controller at the same time. It needs to be scaled to maximum
43 - assigned-clocks: phandle of canfd clock.
44 - assigned-clock-rates: maximum frequency of this clock.
47 The controller can operate in either CAN FD only mode (default) or
50 - renesas,no-can-fd: puts the controller in Classical CAN only mode.
53 -------
58 compatible = "renesas,r8a7795-canfd",
59 "renesas,rcar-gen3-canfd";
66 clock-names = "fck", "canfd", "can_clk";
67 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
68 assigned-clock-rates = <40000000>;
69 power-domains = <&cpg>;
81 Board specific .dts file:
86 pinctrl-0 = <&canfd1_pins>;
87 pinctrl-names = "default";
88 renesas,no-can-fd;
100 pinctrl-0 = <&canfd0_pins &can_clk_pins>;
101 pinctrl-names = "default";