Lines Matching +full:rx +full:- +full:delay +full:- +full:ps
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-emac
19 - const: allwinner,sun8i-v3s-emac
20 - const: allwinner,sun50i-a64-emac
21 - items:
22 - const: allwinner,sun50i-h6-emac
23 - const: allwinner,sun50i-a64-emac
31 interrupt-names:
37 clock-names:
47 - compatible
48 - reg
49 - interrupts
50 - interrupt-names
51 - clocks
52 - clock-names
53 - resets
54 - reset-names
55 - phy-handle
56 - phy-mode
57 - syscon
60 - $ref: "snps,dwmac.yaml#"
61 - if:
66 - allwinner,sun8i-a83t-emac
67 - allwinner,sun8i-h3-emac
68 - allwinner,sun8i-v3s-emac
69 - allwinner,sun50i-a64-emac
73 allwinner,tx-delay-ps:
79 External RGMII PHY TX clock delay chain value in ps.
81 allwinner,rx-delay-ps:
87 External RGMII PHY TX clock delay chain value in ps.
89 - if:
94 - allwinner,sun8i-r40-emac
98 allwinner,rx-delay-ps:
104 External RGMII PHY TX clock delay chain value in ps.
106 - if:
111 - allwinner,sun8i-h3-emac
112 - allwinner,sun8i-v3s-emac
116 allwinner,leds-active-low:
121 mdio-mux:
126 const: allwinner,sun8i-h3-mdio-mux
128 mdio-parent-bus:
138 "#address-cells":
141 "#size-cells":
145 const: allwinner,sun8i-h3-mdio-internal
151 "^ethernet-phy@[0-9a-f]$":
164 - clocks
165 - resets
173 "#address-cells":
176 "#size-cells":
183 - compatible
184 - mdio-parent-bus
185 - mdio@1
190 - |
192 compatible = "allwinner,sun8i-h3-emac";
196 interrupt-names = "macirq";
198 reset-names = "stmmaceth";
200 clock-names = "stmmaceth";
202 phy-handle = <&int_mii_phy>;
203 phy-mode = "mii";
204 allwinner,leds-active-low;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "snps,dwmac-mdio";
212 mdio-mux {
213 compatible = "allwinner,sun8i-h3-mdio-mux";
214 #address-cells = <1>;
215 #size-cells = <0>;
217 mdio-parent-bus = <&mdio1>;
220 compatible = "allwinner,sun8i-h3-mdio-internal";
222 #address-cells = <1>;
223 #size-cells = <0>;
225 ethernet-phy@1 {
229 phy-is-integrated;
235 #address-cells = <1>;
236 #size-cells = <0>;
241 - |
243 compatible = "allwinner,sun8i-h3-emac";
247 interrupt-names = "macirq";
249 reset-names = "stmmaceth";
251 clock-names = "stmmaceth";
253 phy-handle = <&ext_rgmii_phy>;
254 phy-mode = "rgmii";
255 allwinner,leds-active-low;
258 #address-cells = <1>;
259 #size-cells = <0>;
260 compatible = "snps,dwmac-mdio";
263 mdio-mux {
264 compatible = "allwinner,sun8i-h3-mdio-mux";
265 #address-cells = <1>;
266 #size-cells = <0>;
267 mdio-parent-bus = <&mdio2>;
270 compatible = "allwinner,sun8i-h3-mdio-internal";
272 #address-cells = <1>;
273 #size-cells = <0>;
275 ethernet-phy@1 {
284 #address-cells = <1>;
285 #size-cells = <0>;
287 ext_rgmii_phy: ethernet-phy@1 {
294 - |
296 compatible = "allwinner,sun8i-a83t-emac";
300 interrupt-names = "macirq";
302 reset-names = "stmmaceth";
304 clock-names = "stmmaceth";
305 phy-handle = <&ext_rgmii_phy1>;
306 phy-mode = "rgmii";
309 compatible = "snps,dwmac-mdio";
310 #address-cells = <1>;
311 #size-cells = <0>;
313 ext_rgmii_phy1: ethernet-phy@1 {