Lines Matching +full:nand +full:- +full:is +full:- +full:boot +full:- +full:medium
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
24 The interpretation of these parameters is implementation-defined, so
31 pattern: "^nand-controller(@.*)?"
33 "#address-cells":
36 "#size-cells":
42 "^nand@[a-f0-9]$":
49 nand-ecc-mode:
52 embedded in the NAND controller) or software correction
53 (Linux will handle the calculations). soft_bch is deprecated
54 and should be replaced by soft and nand-ecc-algo.
56 enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
58 nand-ecc-engine:
60 - $ref: /schemas/types.yaml#/definitions/phandle
64 1/ The ECC engine is part of the NAND controller, in this
66 2/ The ECC engine is part of the NAND part (on-die), in this
68 3/ The ECC engine is external, in this case the phandle should
71 nand-use-soft-ecc-engine:
75 nand-no-ecc-engine:
79 nand-ecc-placement:
81 - $ref: /schemas/types.yaml#/definitions/string
82 - enum: [ oob, interleaved ]
84 Location of the ECC bytes. This location is unknown by default
89 nand-ecc-algo:
95 nand-bus-width:
97 Bus width to the NAND chip
102 nand-on-flash-bbt:
108 it as the device ages. Otherwise, the out-of-band area of a
109 few pages of all the blocks will be scanned at boot time to
113 nand-ecc-strength:
119 nand-ecc-step-size:
125 nand-ecc-maximize:
129 maximum ECC strength is both controller and chip
132 constraint into account. This is particularly useful when
133 only the in-band area is used by the upper layers, and you
134 want to make your NAND as reliable as possible.
136 nand-is-boot-medium:
139 Whether or not the NAND chip is a boot medium. Drivers might
141 the boot ROM or similar restrictions.
143 nand-rb:
144 $ref: /schemas/types.yaml#/definitions/uint32-array
148 rb-gpios:
152 Ready/Busy pins. Active state refers to the NAND ready state and
153 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
156 - reg
159 - "#address-cells"
160 - "#size-cells"
165 - |
166 nand-controller {
167 #address-cells = <1>;
168 #size-cells = <0>;
172 nand@0 {
174 nand-ecc-mode = "soft";
175 nand-ecc-algo = "bch";