Lines Matching +full:nemc +full:- +full:tah

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Paul Cercueil <paul@crapouillou.net>
13   - $ref: nand-controller.yaml#
18       - ingenic,jz4740-nand
19       - ingenic,jz4725b-nand
20       - ingenic,jz4780-nand
24       - description: Bank number, offset and size of first attached NAND chip
25       - description: Bank number, offset and size of second attached NAND chip
26       - description: Bank number, offset and size of third attached NAND chip
27       - description: Bank number, offset and size of fourth attached NAND chip
30   ecc-engine: true
39   "^nand@[a-f0-9]$":
42       rb-gpios:
46       wp-gpios:
47         description: GPIO specifier for the write-protect pin.
51   - compatible
52   - reg
57   - |
58     #include <dt-bindings/clock/jz4780-cgu.h>
59     memory-controller@13410000 {
60       compatible = "ingenic,jz4780-nemc";
62       #address-cells = <2>;
63       #size-cells = <1>;
73       nand-controller@1 {
74         compatible = "ingenic,jz4780-nand";
77         #address-cells = <1>;
78         #size-cells = <0>;
80         ecc-engine = <&bch>;
82         ingenic,nemc-tAS = <10>;
83         ingenic,nemc-tAH = <5>;
84         ingenic,nemc-tBP = <10>;
85         ingenic,nemc-tAW = <15>;
86         ingenic,nemc-tSTRV = <100>;
88         pinctrl-names = "default";
89         pinctrl-0 = <&pins_nemc>;
94           nand-ecc-step-size = <1024>;
95           nand-ecc-strength = <24>;
96           nand-ecc-mode = "hw";
97           nand-on-flash-bbt;
99           pinctrl-names = "default";
100           pinctrl-0 = <&pins_nemc_cs1>;
103             compatible = "fixed-partitions";
104             #address-cells = <2>;
105             #size-cells = <2>;
108               label = "u-boot-spl";
113               label = "u-boot";
118               label = "u-boot-env";