Lines Matching +full:nand +full:- +full:on +full:- +full:flash +full:- +full:bbt
1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
5 registers and for its data input/output buffer. On some SoCs, this controller is
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
10 available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
17 added on top of the base core controller.
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
26 brcm,brcmnand-v5.0
27 brcm,brcmnand-v6.0
28 brcm,brcmnand-v6.1
29 brcm,brcmnand-v6.2
30 brcm,brcmnand-v7.0
31 brcm,brcmnand-v7.1
32 brcm,brcmnand-v7.2
33 brcm,brcmnand-v7.3
35 - reg : the register start and length for NAND register region.
36 (optional) Flash DMA register range (if present)
37 (optional) NAND flash cache range (if at non-standard offset)
38 - reg-names : a list of the names corresponding to the previous register
39 ranges. Should contain "nand" and (optionally)
40 "flash-dma" or "flash-edu" and/or "nand-cache".
41 - interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available)
43 - interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" or "flash_edu_done",
45 May be "nand", if the SoC has the individual NAND
48 - #address-cells : <1> - subnodes give the chip-select number
49 - #size-cells : <0>
52 - clock : reference to the clock for the NAND controller
53 - clock-names : "nand" (required for the above clock)
54 - brcm,nand-has-wp : Some versions of this IP include a write-protect
55 (WP) control bit. It is always available on >=
59 -- Additional SoC-specific NAND controller properties --
61 The NAND controller is integrated differently on the variety of SoCs on which it
63 with which to control the 8 exposed NAND interrupts, as well as hardware for
64 configuring the endianness of the data bus. On some SoCs, these features are
66 normal IRQ chip), but on others, they are controlled in unique and interesting
67 ways, sometimes with registers that lump multiple NAND-related functions
70 we define additional 'compatible' properties and associated register resources within the NAND cont…
72 - compatible: Can be one of several SoC-specific strings. Each SoC may have
76 * "brcm,nand-bcm63138"
77 - reg: (required) the 'NAND_INT_BASE' register range, with separate status
79 - reg-names: (required) "nand-int-base"
81 * "brcm,nand-bcm6368"
82 - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
83 - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
85 - reg-names: (required) "nand-int-base"
87 * "brcm,nand-iproc"
88 - reg: (required) the "IDM" register range, for interrupt enable and APB
91 - reg-names: (required) a list of the names corresponding to the previous
92 register ranges. Should contain "iproc-idm" and "iproc-ext".
95 * NAND chip-select
98 to represent enabled chip-selects which (may) contain NAND flash chips. Their
102 - compatible : should contain "brcm,nandcs"
103 - reg : a single integer representing the chip-select
105 - #address-cells : see partition.txt
106 - #size-cells : see partition.txt
109 - nand-ecc-strength : see nand-controller.yaml
110 - nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
111 - nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
112 chip-select. See nand-controller.yaml
113 - brcm,nand-oob-sector-size : integer, to denote the spare area sector size
115 addition to the strength and step-size,
117 out the parity bytes it stores on the flash.
119 the flash geometry (particularly the NAND page
121 from NAND, the boot controller has only a limited
125 Each nandcs device node may optionally contain sub-nodes describing the flash
131 nand@f0442800 {
132 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
135 reg-names = "nand", "flash-dma";
136 interrupt-parent = <&hif_intr2_intc>;
139 #address-cells = <1>;
140 #size-cells = <0>;
145 nand-on-flash-bbt;
146 nand-ecc-strength = <12>;
147 nand-ecc-step-size = <512>;
150 #address-cells = <1>; // <2>, for 64-bit offset
151 #size-cells = <1>; // <2>, for 64-bit length
164 nand@10000200 {
165 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
166 "brcm,brcmnand-v4.0", "brcm,brcmnand";
170 reg-names = "nand", "nand-cache", "nand-int-base";
171 interrupt-parent = <&periph_intc>;
174 clock-names = "nand";
176 #address-cells = <1>;
177 #size-cells = <0>;
182 nand-on-flash-bbt;
183 nand-ecc-strength = <1>;
184 nand-ecc-step-size = <512>;