Lines Matching +full:gcc +full:- +full:qcs404
1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
19 "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
20 "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
21 "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
22 "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
23 "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
25 have the string "qcom,sdhci-msm-v4" without the SoC compatible string
28 - reg: Base address and length of the register in the following order:
29 - Host controller register map (required)
30 - SD Core register map (required for controllers earlier than msm-v5)
31 - CQE register map (Optional, CQE support is present on SDHC instance meant
33 - reg-names: When CQE register map is supplied, below reg-names are required
34 - "hc" for Host controller register map
35 - "core" for SD core register map
36 - "cqhci" for CQE register map
37 - interrupts: Should contain an interrupt-specifiers for the interrupts:
38 - Host controller interrupt (required)
39 - pinctrl-names: Should contain only one value - "default".
40 - pinctrl-0: Should specify pin control groups used for this controller.
41 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
42 - clock-names: Should contain the following:
43 "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
44 "core" - SDC MMC clock (MCLK) (required)
45 "bus" - SDCC bus voter clock (optional)
46 "xo" - TCXO clock (optional)
47 "cal" - reference clock for RCLK delay calibration (optional)
48 "sleep" - sleep clock for RCLK delay calibration (optional)
50 - qcom,ddr-config: Certain chipsets and platforms require particular settings
54 - qcom,dll-config: Chipset and Platform specific value. Use this field to
59 - interconnects: Pairs of phandles and interconnect provider specifier
63 - interconnect-names: For sdhc, we have two main paths.
67 is "sdhc-ddr" and for config interconnect path it is
68 "cpu-sdhc".
75 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
78 bus-width = <8>;
79 non-removable;
81 vmmc-supply = <&pm8941_l20>;
82 vqmmc-supply = <&pm8941_s3>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
87 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
88 clock-names = "core", "iface";
91 interconnect-names = "sdhc-ddr","cpu-sdhc";
93 qcom,dll-config = <0x000f642c>;
94 qcom,ddr-config = <0x80040868>;
98 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
101 bus-width = <4>;
102 cd-gpios = <&msmgpio 62 0x1>;
104 vmmc-supply = <&pm8941_l21>;
105 vqmmc-supply = <&pm8941_l13>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
110 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
111 clock-names = "core", "iface";
113 qcom,dll-config = <0x0007642c>;
114 qcom,ddr-config = <0x80040868>;