Lines Matching +full:imx7ulp +full:- +full:usdhc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: "mmc-controller.yaml"
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
30 - fsl,imx6q-usdhc
31 - fsl,imx6sl-usdhc
32 - fsl,imx6sx-usdhc
33 - fsl,imx6ull-usdhc
34 - fsl,imx7d-usdhc
35 - fsl,imx7ulp-usdhc
36 - items:
37 - enum:
38 - fsl,imx8mm-usdhc
39 - fsl,imx8mn-usdhc
40 - fsl,imx8mp-usdhc
41 - fsl,imx8mq-usdhc
42 - fsl,imx8qxp-usdhc
43 - const: fsl,imx7d-usdhc
51 fsl,wp-controller:
56 fsl,delay-line:
62 due to signal path is too long on the board. Please refer to eSDHC/uSDHC
66 voltage-ranges:
67 $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
75 - description: value for minimum slot voltage
76 - description: value for maximum slot voltage
79 fsl,tuning-start-tap:
85 fsl,tuning-step:
89 The uSDHC use one delay cell as default increasing step to do tuning process.
95 fsl,strobe-dll-delay-target:
106 - compatible
107 - reg
108 - interrupts
113 - |
115 compatible = "fsl,imx51-esdhc";
118 fsl,wp-controller;
122 compatible = "fsl,imx51-esdhc";
125 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
126 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */