Lines Matching +full:1 +full:mhz

16   from 1 to 3. If the port mode is not specified, that port is treated
33   ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
40   * "usbhost_120m_fck" - 120MHz Functional clock.
43   * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44   * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45   * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46   * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
48   * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
51   * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52   * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53   * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54   * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55   * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56   * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
60 - #address-cells: Must be 1
61 - #size-cells: Must be 1
76 	#address-cells = <1>;
77 	#size-cells = <1>;