Lines Matching +full:ast2500 +full:- +full:lpc
2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
7 primary use case of the Aspeed LPC controller is as a slave on the bus
11 The LPC controller is represented as a multi-function device to account for the
14 "basically compatible with the [LPC registers from the] popular BMC controller
22 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
23 physical properties of some LPC pins, configuration of serial IRQs, and
24 APB-to-LPC bridging amonst other functions.
26 * An LPC Host Interface Controller: Manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
34 Additionally the state of the LPC controller influences the pinmux
39 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c888374547021…
40 …el.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev…
46 - compatible: One of:
47 "aspeed,ast2400-lpc", "simple-mfd"
48 "aspeed,ast2500-lpc", "simple-mfd"
50 - reg: contains the physical address and length values of the Aspeed
51 LPC memory region.
53 - #address-cells: <1>
54 - #size-cells: <1>
55 - ranges: Maps 0 to the physical address and length of the LPC memory
58 Required LPC Child nodes
62 --------
64 - compatible: One of:
65 "aspeed,ast2400-lpc-bmc"
66 "aspeed,ast2500-lpc-bmc"
68 - reg: contains the physical address and length values of the
69 H8S/2168-compatible LPC controller memory region
72 ---------
74 - compatible: One of:
75 "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
76 "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
78 - reg: contains the address and length values of the host-related
79 register space for the Aspeed LPC controller
81 - #address-cells: <1>
82 - #size-cells: <1>
83 - ranges: Maps 0 to the address and length of the host-related LPC memory
88 lpc: lpc@1e789000 {
89 compatible = "aspeed,ast2500-lpc", "simple-mfd";
92 #address-cells = <1>;
93 #size-cells = <1>;
96 lpc_bmc: lpc-bmc@0 {
97 compatible = "aspeed,ast2500-lpc-bmc";
101 lpc_host: lpc-host@80 {
102 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
104 reg-io-width = <4>;
106 #address-cells = <1>;
107 #size-cells = <1>;
119 LPC Host Interface Controller
120 -------------------
122 The LPC Host Interface Controller manages functions exposed to the host such as
123 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
128 - compatible: One of:
129 "aspeed,ast2400-lpc-ctrl";
130 "aspeed,ast2500-lpc-ctrl";
132 - reg: contains offset/length values of the host interface controller
135 - clocks: contains a phandle to the syscon node describing the clocks.
140 - memory-region: A phandle to a reserved_memory region to be used for the LPC
143 - flash: A phandle to the SPI flash controller containing the flash to
144 be exposed over the LPC to AHB mapping
148 lpc-host@80 {
149 lpc_ctrl: lpc-ctrl@0 {
150 compatible = "aspeed,ast2500-lpc-ctrl";
153 memory-region = <&flash_memory>;
158 LPC Host Controller
159 -------------------
161 The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
163 in the "host" portion of the Aspeed LPC controller, which must be the parent of
164 the LPC host controller node.
168 - compatible: One of:
169 "aspeed,ast2400-lhc";
170 "aspeed,ast2500-lhc";
172 - reg: contains offset/length values of the LHC memory regions. In the
173 AST2400 and AST2500 there are two regions.
178 compatible = "aspeed,ast2500-lhc";
182 LPC reset control
183 -----------------
186 state of the LPC bus. Some systems may chose to modify this configuration.
190 - compatible: "aspeed,ast2500-lpc-reset" or
191 "aspeed,ast2400-lpc-reset"
192 - reg: offset and length of the IP in the LHC memory region
193 - #reset-controller indicates the number of reset cells expected
197 lpc_reset: reset-controller@18 {
198 compatible = "aspeed,ast2500-lpc-reset";
200 #reset-cells = <1>;