Lines Matching full:aspeed
2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
7 primary use case of the Aspeed LPC controller is as a slave on the bus
13 layout at the start of the I/O space which is, to quote the Aspeed datasheet,
47 "aspeed,ast2400-lpc", "simple-mfd"
48 "aspeed,ast2500-lpc", "simple-mfd"
50 - reg: contains the physical address and length values of the Aspeed
65 "aspeed,ast2400-lpc-bmc"
66 "aspeed,ast2500-lpc-bmc"
75 "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
76 "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
79 register space for the Aspeed LPC controller
89 compatible = "aspeed,ast2500-lpc", "simple-mfd";
97 compatible = "aspeed,ast2500-lpc-bmc";
102 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
129 "aspeed,ast2400-lpc-ctrl";
130 "aspeed,ast2500-lpc-ctrl";
150 compatible = "aspeed,ast2500-lpc-ctrl";
161 The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
163 in the "host" portion of the Aspeed LPC controller, which must be the parent of
169 "aspeed,ast2400-lhc";
170 "aspeed,ast2500-lhc";
178 compatible = "aspeed,ast2500-lhc";
185 The UARTs present in the ASPEED SoC can have their resets tied to the reset
190 - compatible: "aspeed,ast2500-lpc-reset" or
191 "aspeed,ast2400-lpc-reset"
198 compatible = "aspeed,ast2500-lpc-reset";