Lines Matching +full:emc +full:- +full:timings +full:-
1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
37 "#reset-cells":
40 "#iommu-cells":
44 "^emc-timings-[0-9]+$":
47 nvidia,ram-code:
53 "^timing-[0-9]+$":
56 clock-frequency:
62 nvidia,emem-configuration:
63 $ref: /schemas/types.yaml#/definitions/uint32-array
68 - description: MC_EMEM_ARB_CFG
69 - description: MC_EMEM_ARB_OUTSTANDING_REQ
70 - description: MC_EMEM_ARB_TIMING_RCD
71 - description: MC_EMEM_ARB_TIMING_RP
72 - description: MC_EMEM_ARB_TIMING_RC
73 - description: MC_EMEM_ARB_TIMING_RAS
74 - description: MC_EMEM_ARB_TIMING_FAW
75 - description: MC_EMEM_ARB_TIMING_RRD
76 - description: MC_EMEM_ARB_TIMING_RAP2PRE
77 - description: MC_EMEM_ARB_TIMING_WAP2PRE
78 - description: MC_EMEM_ARB_TIMING_R2R
79 - description: MC_EMEM_ARB_TIMING_W2W
80 - description: MC_EMEM_ARB_TIMING_R2W
81 - description: MC_EMEM_ARB_TIMING_W2R
82 - description: MC_EMEM_ARB_DA_TURNS
83 - description: MC_EMEM_ARB_DA_COVERS
84 - description: MC_EMEM_ARB_MISC0
85 - description: MC_EMEM_ARB_MISC1
86 - description: MC_EMEM_ARB_RING1_THROTTLE
89 - clock-frequency
90 - nvidia,emem-configuration
95 - nvidia,ram-code
100 - compatible
101 - reg
102 - interrupts
103 - clocks
104 - clock-names
105 - "#reset-cells"
106 - "#iommu-cells"
111 - |
112 memory-controller@70019000 {
113 compatible = "nvidia,tegra124-mc";
116 clock-names = "mc";
120 #iommu-cells = <1>;
121 #reset-cells = <1>;
123 emc-timings-3 {
124 nvidia,ram-code = <3>;
126 timing-12750000 {
127 clock-frequency = <12750000>;
129 nvidia,emem-configuration = <