Lines Matching +full:0 +full:x800000
24 0 <physical address of mapping> <size>
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
53 ALE[0] to the cycle that the first read data is sampled
63 DEV_OEn assertion. If set to 0 (default),
72 de-assertion of DEV_CSn. If set to 0 (default),
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
90 A[2:0] and Data are kept valid as long as DEV_WEn
97 DEV_A[2:0] and Data are kept valid (do not toggle) for
105 0: False
115 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
116 for chip select 0 (a.k.a DEV_BOOTCS).
124 0x10400: DEV_BOOTCS
125 0x10408: DEV_CS0
126 0x10410: DEV_CS1
127 0x10418: DEV_CS2
128 0x10420: DEV_CS3
133 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
142 devbus,badr-skew-ps = <0>;
145 devbus,rd-setup-ps = <0>;
146 devbus,rd-hold-ps = <0>;
149 devbus,sync-enable = <0>;
154 flash@0 {
158 reg = <0 0x1000000>;
167 partition@0 {
169 reg = <0 0x800000>;
174 reg = <0x800000 0x800000>;