Lines Matching +full:imx8mm +full:- +full:ddrc
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
18 switching is implemented by TF-A code which runs from a SRAM area.
20 The Linux driver for the DDRC doesn't even map registers (they're included
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
42 clock-names:
44 - const: core
45 - const: pll
46 - const: alt
47 - const: apb
49 operating-points-v2: true
50 opp-table: true
53 - reg
54 - compatible
55 - clocks
56 - clock-names
61 - |
62 #include <dt-bindings/clock/imx8mm-clock.h>
63 ddrc: memory-controller@3d400000 {
64 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
66 clock-names = "core", "pll", "alt", "apb";
71 operating-points-v2 = <&ddrc_opp_table>;