Lines Matching +full:l2 +full:- +full:data +full:- +full:latency

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11   - Serge Semin <fancer.lancer@gmail.com>
14   By means of the System Controller Baikal-T1 SoC exposes a few settings to
15   tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16   to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17   L2-cache controller block is responsible for the tuning. Its DT node is
22     const: baikal,bt1-l2-ctl
27   baikal,l2-ws-latency:
29     description: Cycles of latency for Way-select RAM accesses
34   baikal,l2-tag-latency:
36     description: Cycles of latency for Tag RAM accesses
41   baikal,l2-data-latency:
43     description: Cycles of latency for Data RAM accesses
51   - compatible
54   - |
55     l2@1f04d028 {
56       compatible = "baikal,bt1-l2-ctl";
59       baikal,l2-ws-latency = <1>;
60       baikal,l2-tag-latency = <1>;
61       baikal,l2-data-latency = <2>;