Lines Matching +full:per +full:- +full:port

1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8   - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9   - reg: base address and size of the memory mapped region
10   - clocks: phandles to the clocks driving the controller
11   - clock-names: must contain:
14     * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18   - phys: phandle to the external D-PHY, phy-names must be provided
19   - phy-names: must contain "dphy", if the implementation uses an
20                external D-PHY
23   - ports: A ports node with one port child node per device input and output
24            port, in accordance with the video interface bindings defined in
25            Documentation/devicetree/bindings/media/video-interfaces.txt. The
26            port nodes are numbered as follows:
28            Port Description
29            -----------------------------
30            0    CSI-2 input
36            The stream output port nodes are optional if they are not
38            in the design.Since there is only one endpoint per port,
44 csi2rx: csi-bridge@0d060000 {
50 	clock-names = "sys_clk", "p_clk",
55 		#address-cells = <1>;
56 		#size-cells = <0>;
58 		port@0 {
62 				remote-endpoint = <&sensor_out_csi2rx>;
63 				clock-lanes = <0>;
64 				data-lanes = <1 2>;
68 		port@1 {
72 				remote-endpoint = <&grabber0_in_csi2rx>;
76 		port@2 {
80 				remote-endpoint = <&grabber1_in_csi2rx>;
84 		port@3 {
88 				remote-endpoint = <&grabber2_in_csi2rx>;
92 		port@4 {
96 				remote-endpoint = <&grabber3_in_csi2rx>;