Lines Matching +full:video +full:- +full:codec

1 Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
5 Each actual codec engines is controlled by a microcontroller (MCU). Host
10   - compatible: value should be one of the following
11     "allegro,al5e-1.1", "allegro,al5e": encoder IP core
12     "allegro,al5d-1.1", "allegro,al5d": decoder IP core
13   - reg: base and length of the memory mapped register region and base and
15   - reg-names: must include "regs" and "sram"
16   - interrupts: shared interrupt from the MCUs to the processing system
17   - clocks: must contain an entry for each entry in clock-names
18   - clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk",
22 	al5e: video-codec@a0009000 {
23 		compatible = "allegro,al5e-1.1", "allegro,al5e";
26 		reg-names = "regs", "sram";
30 		clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
33 	al5d: video-codec@a0029000 {
34 		compatible = "allegro,al5d-1.1", "allegro,al5d";
37 		reg-names = "regs", "sram";
41 		clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",