Lines Matching +full:mmu +full:- +full:500
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sc7180-smmu-v2
32 - qcom,sdm845-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "arm,mmu-500"
37 - enum:
38 - qcom,sc7180-smmu-500
39 - qcom,sdm845-smmu-500
40 - qcom,sm8150-smmu-500
41 - qcom,sm8250-smmu-500
42 - const: arm,mmu-500
43 - description: Marvell SoCs implementing "arm,mmu-500"
45 - const: marvell,ap806-smmu-500
46 - const: arm,mmu-500
47 - description: NVIDIA SoCs that program two ARM MMU-500s identically
49 - enum:
50 - nvidia,tegra194-smmu
51 - const: nvidia,smmu-500
52 - items:
53 - const: arm,mmu-500
54 - const: arm,smmu-v2
55 - items:
56 - enum:
57 - arm,mmu-400
58 - arm,mmu-401
59 - const: arm,smmu-v1
60 - enum:
61 - arm,smmu-v1
62 - arm,smmu-v2
63 - arm,mmu-400
64 - arm,mmu-401
65 - arm,mmu-500
66 - cavium,smmu-v2
72 '#global-interrupts':
76 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
78 '#iommu-cells':
94 Interrupt list, with the first #global-interrupts entries corresponding to
102 dma-coherent:
110 calxeda,smmu-secure-config-access:
114 access to SMMU configuration registers. In this case non-secure aliases of
117 stream-match-mask:
120 For SMMUs supporting stream matching and using #iommu-cells = <1>,
124 Stream ID (e.g. for certain MMU-500 configurations given globally unique
126 using stream matching with #iommu-cells = <2>, and may be ignored if
129 clock-names:
131 - const: bus
132 - const: iface
136 - description: bus clock required for downstream bus access and for the
138 - description: interface clock required to access smmu's registers
141 power-domains:
145 - compatible
146 - reg
147 - '#global-interrupts'
148 - '#iommu-cells'
149 - interrupts
154 - if:
159 - nvidia,tegra194-smmu
171 - |+
174 compatible = "arm,smmu-v1";
176 #global-interrupts = <2>;
183 #iommu-cells = <1>;
195 compatible = "arm,smmu-v1";
197 #global-interrupts = <2>;
204 #iommu-cells = <2>;
219 /* ARM MMU-500 with 10-bit stream ID input configuration */
221 compatible = "arm,mmu-500", "arm,smmu-v2";
223 #global-interrupts = <2>;
230 #iommu-cells = <1>;
231 /* always ignore appended 5-bit TBU number */
232 stream-match-mask = <0x7c00>;
236 /* bus whose child devices emit one unique 10-bit stream
238 iommu-map = <0 &smmu3 0 0x400>;
243 - |+
244 /* Qcom's arm,smmu-v2 implementation */
245 #include <dt-bindings/interrupt-controller/arm-gic.h>
246 #include <dt-bindings/interrupt-controller/irq.h>
248 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
251 #global-interrupts = <1>;
255 #iommu-cells = <1>;
256 power-domains = <&mmcc 0>;
260 clock-names = "bus", "iface";