Lines Matching full:smmu
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
18 The SMMU may also raise interrupts in response to various fault
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sc7180-smmu-v2
32 - qcom,sdm845-smmu-v2
33 - const: qcom,smmu-v2
38 - qcom,sc7180-smmu-500
39 - qcom,sdm845-smmu-500
40 - qcom,sm8150-smmu-500
41 - qcom,sm8250-smmu-500
45 - const: marvell,ap806-smmu-500
50 - nvidia,tegra194-smmu
51 - const: nvidia,smmu-500
54 - const: arm,smmu-v2
59 - const: arm,smmu-v1
61 - arm,smmu-v1
62 - arm,smmu-v2
66 - cavium,smmu-v2
83 by that device into the relevant SMMU.
96 interrupts, specified in order of their indexing by the SMMU.
104 Present if page table walks made by the SMMU are cache coherent with the
107 NOTE: this only applies to the SMMU itself, not masters connected
108 upstream of the SMMU.
110 calxeda,smmu-secure-config-access:
114 access to SMMU configuration registers. In this case non-secure aliases of
115 secure registers have to be used during SMMU configuration.
137 smmu ptw
138 - description: interface clock required to access smmu's registers
159 - nvidia,tegra194-smmu
172 /* SMMU with stream matching or stream indexing */
174 compatible = "arm,smmu-v1";
193 /* SMMU with stream matching */
195 compatible = "arm,smmu-v1";
221 compatible = "arm,mmu-500", "arm,smmu-v2";
237 ID each, but may master through multiple SMMU TBUs */
244 /* Qcom's arm,smmu-v2 implementation */
248 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";